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https://gitlab.com/qemu-project/qemu
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318df7238b
Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22 lines
1.0 KiB
Meson
22 lines
1.0 KiB
Meson
common_ss.add(when: 'CONFIG_ALPHA_DIS', if_true: files('alpha.c'))
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common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c'))
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common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c'))
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common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
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common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
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common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c'))
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common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
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common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c'))
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common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
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'riscv.c',
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'riscv-xthead.c',
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'riscv-xventana.c'
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))
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common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
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common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
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common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))
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common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone])
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common_ss.add(files('disas.c'))
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system_ss.add(files('disas-mon.c'))
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specific_ss.add(capstone)
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