Richard Henderson 39db007eda target/microblaze: Fix width of EDR ... The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2020-09-01 07:41:38 -07:00
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cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu-qom.h	cpu: Use DeviceClass reset instead of a special CPUClass reset	2020-03-17 19:48:10 -04:00
cpu.c	target/microblaze: Split out MSR from env->sregs	2020-09-01 07:41:38 -07:00
cpu.h	target/microblaze: Fix width of EDR	2020-09-01 07:41:38 -07:00
gdbstub.c	target/microblaze: Split out EDR from env->sregs	2020-09-01 07:41:38 -07:00
helper.c	target/microblaze: Fix width of ESR	2020-09-01 07:41:38 -07:00
helper.h	target-microblaze: Add support for extended access to TLBLO	2018-05-29 09:35:14 +02:00
meson.build	meson: target	2020-08-21 06:30:35 -04:00
microblaze-decode.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
mmu.c	target/microblaze: Fix width of PC and BTARGET	2020-09-01 07:41:38 -07:00
mmu.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
op_helper.c	target/microblaze: Fix width of ESR	2020-09-01 07:41:38 -07:00
translate.c	target/microblaze: Fix width of EDR	2020-09-01 07:41:38 -07:00