qemu/target
Richard Henderson 3944d58db3 target/arm: Assert immh != 0 in disas_simd_shift_imm
Coverity raised a shed-load of errors cascading from inferring
that clz32(immh) might yield 32, from immh might be 0.

While immh cannot be 0 from encoding, it is not obvious even to
a human how we've checked that: via the filtering provided by
data_proc_simd[].

Reported-by: Coverity (CID 1421923, and more)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200320160622.8040-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-23 17:22:30 +00:00
..
alpha x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
arm target/arm: Assert immh != 0 in disas_simd_shift_imm 2020-03-23 17:22:30 +00:00
cris x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
hppa x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
i386 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
lm32 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
m68k x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
microblaze x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
mips x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
moxie cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
nios2 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
openrisc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
ppc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
riscv x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
rx target/rx: Dump bytes for each insn during disassembly 2020-03-19 17:58:05 +01:00
s390x x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
sh4 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
sparc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
tilegx cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
tricore cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
unicore32 tcg: Search includes from the project root source directory 2020-01-15 15:13:10 -10:00
xtensa x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00