mirror of
https://gitlab.com/qemu-project/qemu
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fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
69 lines
1.5 KiB
C
69 lines
1.5 KiB
C
#ifndef STRONGARM_H
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#define STRONGARM_H
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#include "exec/memory.h"
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#include "target/arm/cpu-qom.h"
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#define SA_CS0 0x00000000
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#define SA_CS1 0x08000000
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#define SA_CS2 0x10000000
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#define SA_CS3 0x18000000
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#define SA_PCMCIA_CS0 0x20000000
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#define SA_PCMCIA_CS1 0x30000000
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#define SA_CS4 0x40000000
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#define SA_CS5 0x48000000
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/* system registers here */
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#define SA_SDCS0 0xc0000000
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#define SA_SDCS1 0xc8000000
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#define SA_SDCS2 0xd0000000
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#define SA_SDCS3 0xd8000000
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enum {
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SA_PIC_GPIO0_EDGE = 0,
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SA_PIC_GPIO1_EDGE,
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SA_PIC_GPIO2_EDGE,
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SA_PIC_GPIO3_EDGE,
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SA_PIC_GPIO4_EDGE,
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SA_PIC_GPIO5_EDGE,
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SA_PIC_GPIO6_EDGE,
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SA_PIC_GPIO7_EDGE,
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SA_PIC_GPIO8_EDGE,
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SA_PIC_GPIO9_EDGE,
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SA_PIC_GPIO10_EDGE,
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SA_PIC_GPIOX_EDGE,
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SA_PIC_LCD,
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SA_PIC_UDC,
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SA_PIC_RSVD1,
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SA_PIC_UART1,
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SA_PIC_UART2,
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SA_PIC_UART3,
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SA_PIC_MCP,
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SA_PIC_SSP,
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SA_PIC_DMA_CH0,
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SA_PIC_DMA_CH1,
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SA_PIC_DMA_CH2,
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SA_PIC_DMA_CH3,
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SA_PIC_DMA_CH4,
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SA_PIC_DMA_CH5,
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SA_PIC_OSTC0,
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SA_PIC_OSTC1,
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SA_PIC_OSTC2,
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SA_PIC_OSTC3,
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SA_PIC_RTC_HZ,
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SA_PIC_RTC_ALARM,
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};
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typedef struct {
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ARMCPU *cpu;
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MemoryRegion sdram;
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DeviceState *pic;
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DeviceState *gpio;
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DeviceState *ppc;
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DeviceState *ssp;
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SSIBus *ssp_bus;
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} StrongARMState;
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StrongARMState *sa1110_init(MemoryRegion *sysmem,
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unsigned int sdram_size, const char *rev);
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#endif
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