mirror of
https://gitlab.com/qemu-project/qemu
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b6f54b31e7
Port 0x0092 is documented as read/write, so for now return the endianness state instead of hardcoded 0x00. Signed-off-by: Julio Guerra <guerr@julio.in> [AF: Extracted from larger port 0092 patch] Signed-off-by: Andreas Färber <andreas.faerber@web.de>
692 lines
20 KiB
C
692 lines
20 KiB
C
/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h"
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#include "hw/timer/m48t59.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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#include "hw/block/fdc.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "hw/isa/isa.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/ppc.h"
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#include "hw/boards.h"
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#include "qemu/log.h"
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#include "hw/ide.h"
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#include "hw/loader.h"
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#include "hw/timer/mc146818rtc.h"
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#include "hw/isa/pc87312.h"
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#include "sysemu/blockdev.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/qtest.h"
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#include "exec/address-spaces.h"
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#include "elf.h"
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//#define HARD_DEBUG_PPC_IO
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//#define DEBUG_PPC_IO
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1
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#define MAX_IDE_BUS 2
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#define BIOS_SIZE (1024 * 1024)
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#define BIOS_FILENAME "ppc_rom.bin"
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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#define DEBUG_PPC_IO
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#endif
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#if defined (HARD_DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, ...) \
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do { \
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if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
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qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
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} else { \
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printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
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} \
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} while (0)
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#elif defined (DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, ...) \
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qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
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#else
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#define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
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#endif
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 13, 13 };
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#define NE2000_NB_MAX 6
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000
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/* PowerPC control and status registers */
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#if 0 // Not used
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static struct {
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/* IDs */
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uint32_t veni_devi;
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uint32_t revi;
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/* Control and status */
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uint32_t gcsr;
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uint32_t xcfr;
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uint32_t ct32;
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uint32_t mcsr;
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/* General purpose registers */
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uint32_t gprg[6];
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/* Exceptions */
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uint32_t feen;
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uint32_t fest;
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uint32_t fema;
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uint32_t fecl;
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uint32_t eeen;
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uint32_t eest;
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uint32_t eecl;
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uint32_t eeint;
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uint32_t eemck0;
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uint32_t eemck1;
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/* Error diagnostic */
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} XCSR;
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static void PPC_XCSR_writeb (void *opaque,
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hwaddr addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static void PPC_XCSR_writew (void *opaque,
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hwaddr addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static void PPC_XCSR_writel (void *opaque,
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hwaddr addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static const MemoryRegionOps PPC_XCSR_ops = {
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.old_mmio = {
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.read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
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.write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#endif
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t {
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qemu_irq reset_irq;
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M48t59State *nvram;
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uint8_t state;
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uint8_t syscontrol;
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int contiguous_map;
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int endian;
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} sysctrl_t;
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enum {
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STATE_HARDFILE = 0x01,
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};
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static sysctrl_t *sysctrl;
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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{
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
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addr - PPC_IO_BASE, val);
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) {
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qemu_irq_raise(sysctrl->reset_irq);
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} else {
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qemu_irq_lower(sysctrl->reset_irq);
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}
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/* Check LE mode */
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if (val & 0x02) {
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sysctrl->endian = 1;
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} else {
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sysctrl->endian = 0;
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}
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break;
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case 0x0800:
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802:
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803:
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/* Motorola base module status register : read-only */
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break;
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case 0x0808:
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/* Hardfile light register */
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if (val & 1)
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sysctrl->state |= STATE_HARDFILE;
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else
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sysctrl->state &= ~STATE_HARDFILE;
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break;
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case 0x0810:
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 1);
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break;
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case 0x0812:
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 2);
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break;
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case 0x0814:
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/* L2 invalidate register */
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C:
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
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case 0x0850:
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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" => %02" PRIx32"\n", addr, val);
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break;
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}
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}
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t retval = 0xFF;
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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retval = sysctrl->endian << 1;
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break;
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case 0x0800:
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/* Motorola CPU configuration register */
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retval = 0xEF; /* MPC750 */
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break;
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case 0x0802:
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/* Motorola Base module feature register */
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retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
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break;
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case 0x0803:
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/* Motorola base module status register */
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retval = 0xE0; /* Standard MPC750 */
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break;
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case 0x080C:
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/* Equipment present register:
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* no L2 cache
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* no upgrade processor
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* no cards in PCI slots
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* SCSI fuse is bad
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*/
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retval = 0x3C;
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break;
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case 0x0810:
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/* Motorola base module extended feature register */
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retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
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break;
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case 0x0814:
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/* L2 invalidate: don't care */
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break;
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case 0x0818:
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/* Keylock */
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retval = 0x00;
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break;
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case 0x081C:
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/* system control register
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* 7 - 6 / 1 - 0: L2 cache enable
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*/
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retval = sysctrl->syscontrol;
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break;
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case 0x0823:
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/* */
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retval = 0x03; /* no L2 cache */
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break;
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case 0x0850:
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/* I/O map type register */
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retval = sysctrl->contiguous_map;
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break;
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default:
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printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
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break;
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}
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PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
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addr - PPC_IO_BASE, retval);
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return retval;
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}
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static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
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hwaddr addr)
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{
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if (sysctrl->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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return addr;
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}
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static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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cpu_outb(addr, value);
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}
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static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inb(addr);
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return ret;
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}
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static void PPC_prep_io_writew (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outw(addr, value);
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}
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static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inw(addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
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return ret;
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}
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static void PPC_prep_io_writel (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outl(addr, value);
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}
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static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inl(addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
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return ret;
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}
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static const MemoryRegionOps PPC_prep_io_ops = {
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.old_mmio = {
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.read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
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.write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define NVRAM_SIZE 0x2000
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static void cpu_request_exit(void *opaque, int irq, int level)
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{
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CPUPPCState *env = cpu_single_env;
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if (env && level) {
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cpu_exit(env);
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}
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}
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static void ppc_prep_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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/* Reset address */
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cpu->env.nip = 0xfffffffc;
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}
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/* PowerPC PREP hardware initialisation */
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static void ppc_prep_init(QEMUMachineInitArgs *args)
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{
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ram_addr_t ram_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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const char *boot_device = args->boot_device;
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MemoryRegion *sysmem = get_system_memory();
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PowerPCCPU *cpu = NULL;
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CPUPPCState *env = NULL;
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char *filename;
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nvram_t nvram;
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M48t59State *m48t59;
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MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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#endif
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int linux_boot, i, nb_nics1, bios_size;
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *bios = g_new(MemoryRegion, 1);
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uint32_t kernel_base, initrd_base;
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long kernel_size, initrd_size;
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DeviceState *dev;
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PCIHostState *pcihost;
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PCIBus *pci_bus;
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PCIDevice *pci;
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ISABus *isa_bus;
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ISADevice *isa;
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qemu_irq *cpu_exit_irq;
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int ppc_boot_device;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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sysctrl = g_malloc0(sizeof(sysctrl_t));
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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if (cpu_model == NULL)
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cpu_model = "602";
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for (i = 0; i < smp_cpus; i++) {
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cpu = cpu_ppc_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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exit(1);
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}
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env = &cpu->env;
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if (env->flags & POWERPC_FLAG_RTC_CLK) {
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/* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
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cpu_ppc_tb_init(env, 7812500UL);
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} else {
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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}
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qemu_register_reset(ppc_prep_reset, cpu);
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}
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/* allocate RAM */
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memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
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vmstate_register_ram_global(ram);
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memory_region_add_subregion(sysmem, 0, ram);
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|
|
/* allocate and load BIOS */
|
|
memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
|
|
memory_region_set_readonly(bios, true);
|
|
memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios);
|
|
vmstate_register_ram_global(bios);
|
|
if (bios_name == NULL)
|
|
bios_name = BIOS_FILENAME;
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
if (filename) {
|
|
bios_size = load_elf(filename, NULL, NULL, NULL,
|
|
NULL, NULL, 1, ELF_MACHINE, 0);
|
|
if (bios_size < 0) {
|
|
bios_size = get_image_size(filename);
|
|
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
|
|
hwaddr bios_addr;
|
|
bios_size = (bios_size + 0xfff) & ~0xfff;
|
|
bios_addr = (uint32_t)(-bios_size);
|
|
bios_size = load_image_targphys(filename, bios_addr, bios_size);
|
|
}
|
|
if (bios_size > BIOS_SIZE) {
|
|
fprintf(stderr, "qemu: PReP bios '%s' is too large (0x%x)\n",
|
|
bios_name, bios_size);
|
|
exit(1);
|
|
}
|
|
}
|
|
} else {
|
|
bios_size = -1;
|
|
}
|
|
if (bios_size < 0 && !qtest_enabled()) {
|
|
fprintf(stderr, "qemu: could not load PPC PReP bios '%s'\n",
|
|
bios_name);
|
|
exit(1);
|
|
}
|
|
if (filename) {
|
|
g_free(filename);
|
|
}
|
|
|
|
if (linux_boot) {
|
|
kernel_base = KERNEL_LOAD_ADDR;
|
|
/* now we can load the kernel */
|
|
kernel_size = load_image_targphys(kernel_filename, kernel_base,
|
|
ram_size - kernel_base);
|
|
if (kernel_size < 0) {
|
|
hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
|
|
exit(1);
|
|
}
|
|
/* load initrd */
|
|
if (initrd_filename) {
|
|
initrd_base = INITRD_LOAD_ADDR;
|
|
initrd_size = load_image_targphys(initrd_filename, initrd_base,
|
|
ram_size - initrd_base);
|
|
if (initrd_size < 0) {
|
|
hw_error("qemu: could not load initial ram disk '%s'\n",
|
|
initrd_filename);
|
|
}
|
|
} else {
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
}
|
|
ppc_boot_device = 'm';
|
|
} else {
|
|
kernel_base = 0;
|
|
kernel_size = 0;
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
ppc_boot_device = '\0';
|
|
/* For now, OHW cannot boot from the network. */
|
|
for (i = 0; boot_device[i] != '\0'; i++) {
|
|
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
|
|
ppc_boot_device = boot_device[i];
|
|
break;
|
|
}
|
|
}
|
|
if (ppc_boot_device == '\0') {
|
|
fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
|
hw_error("Only 6xx bus is supported on PREP machine\n");
|
|
}
|
|
|
|
dev = qdev_create(NULL, "raven-pcihost");
|
|
pcihost = PCI_HOST_BRIDGE(dev);
|
|
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
|
|
qdev_init_nofail(dev);
|
|
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
|
if (pci_bus == NULL) {
|
|
fprintf(stderr, "Couldn't create PCI host controller.\n");
|
|
exit(1);
|
|
}
|
|
|
|
/* PCI -> ISA bridge */
|
|
pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
|
|
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
|
|
qdev_connect_gpio_out(&pci->qdev, 0,
|
|
first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
|
|
qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
|
|
sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
|
|
sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
|
|
sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
|
|
sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
|
|
isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
|
|
|
|
/* Super I/O (parallel + serial ports) */
|
|
isa = isa_create(isa_bus, TYPE_PC87312);
|
|
qdev_prop_set_uint8(&isa->qdev, "config", 13); /* fdc, ser0, ser1, par0 */
|
|
qdev_init_nofail(&isa->qdev);
|
|
|
|
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
|
memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
|
|
"ppc-io", 0x00800000);
|
|
memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
|
|
|
|
/* init basic PC hardware */
|
|
pci_vga_init(pci_bus);
|
|
|
|
nb_nics1 = nb_nics;
|
|
if (nb_nics1 > NE2000_NB_MAX)
|
|
nb_nics1 = NE2000_NB_MAX;
|
|
for(i = 0; i < nb_nics1; i++) {
|
|
if (nd_table[i].model == NULL) {
|
|
nd_table[i].model = g_strdup("ne2k_isa");
|
|
}
|
|
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
|
|
isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
|
|
&nd_table[i]);
|
|
} else {
|
|
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
|
|
}
|
|
}
|
|
|
|
ide_drive_get(hd, MAX_IDE_BUS);
|
|
for(i = 0; i < MAX_IDE_BUS; i++) {
|
|
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
|
|
hd[2 * i],
|
|
hd[2 * i + 1]);
|
|
}
|
|
isa_create_simple(isa_bus, "i8042");
|
|
|
|
sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
|
|
/* System control ports */
|
|
register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
|
|
register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
|
|
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
|
|
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
|
|
/* PowerPC control and status register group */
|
|
#if 0
|
|
memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
|
|
memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
|
|
#endif
|
|
|
|
if (usb_enabled(false)) {
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
|
}
|
|
|
|
m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
|
|
if (m48t59 == NULL)
|
|
return;
|
|
sysctrl->nvram = m48t59;
|
|
|
|
/* Initialise NVRAM */
|
|
nvram.opaque = m48t59;
|
|
nvram.read_fn = &m48t59_read;
|
|
nvram.write_fn = &m48t59_write;
|
|
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
|
kernel_base, kernel_size,
|
|
kernel_cmdline,
|
|
initrd_base, initrd_size,
|
|
/* XXX: need an option to load a NVRAM image */
|
|
0,
|
|
graphic_width, graphic_height, graphic_depth);
|
|
|
|
/* Special port to get debug messages from Open-Firmware */
|
|
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
|
|
}
|
|
|
|
static QEMUMachine prep_machine = {
|
|
.name = "prep",
|
|
.desc = "PowerPC PREP platform",
|
|
.init = ppc_prep_init,
|
|
.max_cpus = MAX_CPUS,
|
|
DEFAULT_MACHINE_OPTIONS,
|
|
};
|
|
|
|
static void prep_machine_init(void)
|
|
{
|
|
qemu_register_machine(&prep_machine);
|
|
}
|
|
|
|
machine_init(prep_machine_init);
|