Frank Chang 3479a814e4 target/riscv: rvv-1.0: add VMA and VTA ... Introduce vma and vta fields in vtype register. According to RVV 1.0 spec (section 3.3.3): When a set is marked agnostic, the corresponding set of destination elements in any vector or mask destination operand can either retain the value they previously held, or are overwritten with 1s. So, either vta/vma is set to undisturbed or agnostic, it's legal to retain the inactive masked-off elements and tail elements' original values unchanged. Therefore, besides declaring vta/vma fields in vtype register, also remove all the tail elements clean functions in this commit. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-15-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-12-20 14:51:36 +10:00
..
insn_trans	target/riscv: rvv-1.0: remove MLEN calculations	2021-12-20 14:51:36 +10:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
bitmanip_helper.c	target/riscv: Add rev8 instruction, removing grev/grevi	2021-10-07 08:41:33 +10:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: drop vector 0.7.1 and add 1.0 support	2021-12-20 14:51:36 +10:00
cpu.h	target/riscv: rvv-1.0: add VMA and VTA	2021-12-20 14:51:36 +10:00
cpu_bits.h	target/riscv: rvv-1.0: add vlenb register	2021-12-20 14:51:36 +10:00
cpu_helper.c	target/riscv: rvv-1.0: add translation-time vector context status	2021-12-20 14:51:36 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers	2021-12-20 14:51:36 +10:00
fpu_helper.c	target/riscv: zfh: half-precision floating-point classify	2021-12-20 14:51:36 +10:00
gdbstub.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
helper.h	target/riscv: zfh: half-precision floating-point classify	2021-12-20 14:51:36 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: zfh: half-precision floating-point classify	2021-12-20 14:51:36 +10:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: rvv-1.0: remove MLEN calculations	2021-12-20 14:51:36 +10:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
machine.c	target/riscv: machine: Sort the .subsections	2021-11-17 19:18:22 +10:00
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
op_helper.c	target/riscv: Reorg csr instructions	2021-09-01 11:59:12 +10:00
pmp.c	target/riscv: pmp: Fix some typos	2021-07-15 08:56:00 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: rvv-1.0: add fractional LMUL	2021-12-20 14:51:36 +10:00
vector_helper.c	target/riscv: rvv-1.0: add VMA and VTA	2021-12-20 14:51:36 +10:00