qemu/include/hw/ssi
Cédric Le Goater fcdf2c5945 aspeed/smc: handle SPI flash Command mode
The Aspeed SMC controllers have a mode (Command mode) in which
accesses to the flash content are no different than doing MMIOs. The
controller generates all the necessary commands to load (or store)
data in memory.

However, accesses are restricted to the segment window assigned the
the flash module by the controller. This window is defined by the
Segment Address Register.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1483979087-32663-8-git-send-email-clg@kaod.org
[PMM: Deleted now-unused aspeed_smc_is_usermode() function]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-20 11:15:08 +00:00
..
aspeed_smc.h aspeed/smc: handle SPI flash Command mode 2017-01-20 11:15:08 +00:00
imx_spi.h i.MX: Add the Freescale SPI Controller 2016-05-12 13:22:29 +01:00
ssi.h ssi: change ssi_slave_init to be a realize ops 2016-07-04 13:15:22 +01:00
stm32f2xx_spi.h STM32F2xx: Add the SPI device 2016-10-04 13:28:07 +01:00
xilinx_spips.h Clean up header guards that don't match their file name 2016-07-12 16:19:16 +02:00