mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-02 22:41:07 +00:00
376 lines
10 KiB
Python
Executable file
376 lines
10 KiB
Python
Executable file
#! /usr/bin/env python3
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# Generate test-avx.h from x86.csv
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import csv
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import sys
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from fnmatch import fnmatch
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archs = [
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"SSE", "SSE2", "SSE3", "SSSE3", "SSE4_1", "SSE4_2",
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"AES", "AVX", "AVX2", "AES+AVX", "VAES+AVX",
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"F16C", "FMA", "SHA",
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]
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ignore = set(["FISTTP",
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"LDMXCSR", "VLDMXCSR", "STMXCSR", "VSTMXCSR"])
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imask = {
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'vBLENDPD': 0xff,
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'vBLENDPS': 0x0f,
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'CMP[PS][SD]': 0x07,
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'VCMP[PS][SD]': 0x1f,
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'vCVTPS2PH': 0x7,
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'vDPPD': 0x33,
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'vDPPS': 0xff,
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'vEXTRACTPS': 0x03,
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'vINSERTPS': 0xff,
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'MPSADBW': 0x7,
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'VMPSADBW': 0x3f,
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'vPALIGNR': 0x3f,
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'vPBLENDW': 0xff,
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'vPCMP[EI]STR*': 0x0f,
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'vPEXTRB': 0x0f,
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'vPEXTRW': 0x07,
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'vPEXTRD': 0x03,
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'vPEXTRQ': 0x01,
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'vPINSRB': 0x0f,
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'vPINSRW': 0x07,
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'vPINSRD': 0x03,
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'vPINSRQ': 0x01,
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'vPSHUF[DW]': 0xff,
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'vPSHUF[LH]W': 0xff,
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'vPS[LR][AL][WDQ]': 0x3f,
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'vPS[RL]LDQ': 0x1f,
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'vROUND[PS][SD]': 0x7,
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'SHA1RNDS4': 0x03,
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'vSHUFPD': 0x0f,
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'vSHUFPS': 0xff,
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'vAESKEYGENASSIST': 0xff,
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'VEXTRACT[FI]128': 0x01,
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'VINSERT[FI]128': 0x01,
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'VPBLENDD': 0xff,
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'VPERM2[FI]128': 0xbb,
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'VPERMPD': 0xff,
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'VPERMQ': 0xff,
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'VPERMILPS': 0xff,
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'VPERMILPD': 0x0f,
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}
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def strip_comments(x):
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for l in x:
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if l != '' and l[0] != '#':
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yield l
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def reg_w(w):
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if w == 8:
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return 'al'
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elif w == 16:
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return 'ax'
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elif w == 32:
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return 'eax'
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elif w == 64:
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return 'rax'
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raise Exception("bad reg_w %d" % w)
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def mem_w(w):
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if w == 8:
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t = "BYTE"
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elif w == 16:
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t = "WORD"
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elif w == 32:
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t = "DWORD"
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elif w == 64:
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t = "QWORD"
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elif w == 128:
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t = "XMMWORD"
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elif w == 256:
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t = "YMMWORD"
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else:
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raise Exception()
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return t + " PTR 32[rdx]"
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class XMMArg():
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isxmm = True
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def __init__(self, reg, mw):
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if mw not in [0, 8, 16, 32, 64, 128, 256]:
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raise Exception("Bad /m width: %s" % w)
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self.reg = reg
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self.mw = mw
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self.ismem = mw != 0
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def regstr(self, n):
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if n < 0:
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return mem_w(self.mw)
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else:
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return "%smm%d" % (self.reg, n)
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class MMArg():
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isxmm = True
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def __init__(self, mw):
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if mw not in [0, 32, 64]:
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raise Exception("Bad mem width: %s" % mw)
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self.mw = mw
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self.ismem = mw != 0
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def regstr(self, n):
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return "mm%d" % (n & 7)
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def match(op, pattern):
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if pattern[0] == 'v':
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return fnmatch(op, pattern[1:]) or fnmatch(op, 'V'+pattern[1:])
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return fnmatch(op, pattern)
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class ArgVSIB():
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isxmm = True
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ismem = False
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def __init__(self, reg, w):
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if w not in [32, 64]:
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raise Exception("Bad vsib width: %s" % w)
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self.w = w
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self.reg = reg
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def regstr(self, n):
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reg = "%smm%d" % (self.reg, n >> 2)
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return "[rsi + %s * %d]" % (reg, 1 << (n & 3))
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class ArgImm8u():
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isxmm = False
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ismem = False
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def __init__(self, op):
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for k, v in imask.items():
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if match(op, k):
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self.mask = imask[k];
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return
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raise Exception("Unknown immediate")
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def vals(self):
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mask = self.mask
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yield 0
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n = 0
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while n != mask:
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n += 1
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while (n & ~mask) != 0:
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n += (n & ~mask)
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yield n
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class ArgRM():
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isxmm = False
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def __init__(self, rw, mw):
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if rw not in [8, 16, 32, 64]:
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raise Exception("Bad r/w width: %s" % w)
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if mw not in [0, 8, 16, 32, 64]:
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raise Exception("Bad r/w width: %s" % w)
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self.rw = rw
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self.mw = mw
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self.ismem = mw != 0
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def regstr(self, n):
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if n < 0:
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return mem_w(self.mw)
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else:
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return reg_w(self.rw)
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class ArgMem():
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isxmm = False
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ismem = True
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def __init__(self, w):
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if w not in [8, 16, 32, 64, 128, 256]:
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raise Exception("Bad mem width: %s" % w)
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self.w = w
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def regstr(self, n):
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return mem_w(self.w)
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class SkipInstruction(Exception):
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pass
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def ArgGenerator(arg, op):
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if arg[:3] == 'xmm' or arg[:3] == "ymm":
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if "/" in arg:
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r, m = arg.split('/')
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if (m[0] != 'm'):
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raise Exception("Expected /m: %s", arg)
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return XMMArg(arg[0], int(m[1:]));
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else:
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return XMMArg(arg[0], 0);
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elif arg[:2] == 'mm':
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if "/" in arg:
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r, m = arg.split('/')
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if (m[0] != 'm'):
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raise Exception("Expected /m: %s", arg)
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return MMArg(int(m[1:]));
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else:
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return MMArg(0);
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elif arg[:4] == 'imm8':
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return ArgImm8u(op);
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elif arg == '<XMM0>':
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return None
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elif arg[0] == 'r':
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if '/m' in arg:
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r, m = arg.split('/')
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if (m[0] != 'm'):
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raise Exception("Expected /m: %s", arg)
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mw = int(m[1:])
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if r == 'r':
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rw = mw
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else:
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rw = int(r[1:])
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return ArgRM(rw, mw)
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return ArgRM(int(arg[1:]), 0);
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elif arg[0] == 'm':
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return ArgMem(int(arg[1:]))
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elif arg[:2] == 'vm':
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return ArgVSIB(arg[-1], int(arg[2:-1]))
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else:
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raise Exception("Unrecognised arg: %s", arg)
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class InsnGenerator:
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def __init__(self, op, args):
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self.op = op
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if op[-2:] in ["PH", "PS", "PD", "SS", "SD"]:
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if op[-1] == 'H':
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self.optype = 'F16'
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elif op[-1] == 'S':
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self.optype = 'F32'
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else:
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self.optype = 'F64'
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else:
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self.optype = 'I'
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try:
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self.args = list(ArgGenerator(a, op) for a in args)
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if not any((x.isxmm for x in self.args)):
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raise SkipInstruction
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if len(self.args) > 0 and self.args[-1] is None:
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self.args = self.args[:-1]
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except SkipInstruction:
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raise
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except Exception as e:
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raise Exception("Bad arg %s: %s" % (op, e))
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def gen(self):
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regs = (10, 11, 12)
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dest = 9
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nreg = len(self.args)
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if nreg == 0:
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yield self.op
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return
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if isinstance(self.args[-1], ArgImm8u):
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nreg -= 1
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immarg = self.args[-1]
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else:
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immarg = None
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memarg = -1
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for n, arg in enumerate(self.args):
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if arg.ismem:
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memarg = n
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if (self.op.startswith("VGATHER") or self.op.startswith("VPGATHER")):
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if "GATHERD" in self.op:
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ireg = 13 << 2
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else:
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ireg = 14 << 2
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regset = [
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(dest, ireg | 0, regs[0]),
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(dest, ireg | 1, regs[0]),
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(dest, ireg | 2, regs[0]),
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(dest, ireg | 3, regs[0]),
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]
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if memarg >= 0:
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raise Exception("vsib with memory: %s" % self.op)
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elif nreg == 1:
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regset = [(regs[0],)]
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if memarg == 0:
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regset += [(-1,)]
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elif nreg == 2:
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regset = [
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(regs[0], regs[1]),
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(regs[0], regs[0]),
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]
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if memarg == 0:
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regset += [(-1, regs[0])]
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elif memarg == 1:
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regset += [(dest, -1)]
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elif nreg == 3:
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regset = [
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(dest, regs[0], regs[1]),
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(dest, regs[0], regs[0]),
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(regs[0], regs[0], regs[1]),
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(regs[0], regs[1], regs[0]),
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(regs[0], regs[0], regs[0]),
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]
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if memarg == 2:
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regset += [
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(dest, regs[0], -1),
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(regs[0], regs[0], -1),
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]
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elif memarg > 0:
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raise Exception("Memarg %d" % memarg)
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elif nreg == 4:
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regset = [
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(dest, regs[0], regs[1], regs[2]),
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(dest, regs[0], regs[0], regs[1]),
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(dest, regs[0], regs[1], regs[0]),
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(dest, regs[1], regs[0], regs[0]),
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(dest, regs[0], regs[0], regs[0]),
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(regs[0], regs[0], regs[1], regs[2]),
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(regs[0], regs[1], regs[0], regs[2]),
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(regs[0], regs[1], regs[2], regs[0]),
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(regs[0], regs[0], regs[0], regs[1]),
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(regs[0], regs[0], regs[1], regs[0]),
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(regs[0], regs[1], regs[0], regs[0]),
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(regs[0], regs[0], regs[0], regs[0]),
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]
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if memarg == 2:
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regset += [
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(dest, regs[0], -1, regs[1]),
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(dest, regs[0], -1, regs[0]),
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(regs[0], regs[0], -1, regs[1]),
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(regs[0], regs[1], -1, regs[0]),
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(regs[0], regs[0], -1, regs[0]),
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]
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elif memarg > 0:
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raise Exception("Memarg4 %d" % memarg)
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else:
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raise Exception("Too many regs: %s(%d)" % (self.op, nreg))
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for regv in regset:
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argstr = []
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for i in range(nreg):
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arg = self.args[i]
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argstr.append(arg.regstr(regv[i]))
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if immarg is None:
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yield self.op + ' ' + ','.join(argstr)
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else:
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for immval in immarg.vals():
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yield self.op + ' ' + ','.join(argstr) + ',' + str(immval)
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def split0(s):
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if s == '':
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return []
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return s.split(',')
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def main():
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n = 0
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if len(sys.argv) != 3:
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print("Usage: test-avx.py x86.csv test-avx.h")
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exit(1)
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csvfile = open(sys.argv[1], 'r', newline='')
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with open(sys.argv[2], "w") as outf:
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outf.write("// Generated by test-avx.py. Do not edit.\n")
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for row in csv.reader(strip_comments(csvfile)):
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insn = row[0].replace(',', '').split()
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if insn[0] in ignore:
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continue
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cpuid = row[6]
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if cpuid in archs:
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try:
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g = InsnGenerator(insn[0], insn[1:])
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for insn in g.gen():
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outf.write('TEST(%d, "%s", %s)\n' % (n, insn, g.optype))
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n += 1
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except SkipInstruction:
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pass
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outf.write("#undef TEST\n")
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csvfile.close()
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if __name__ == "__main__":
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main()
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