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6494d2c1fd
Some of the PMU hflags bits can go out of synch, for example a store to
MMCR0 with PMCjCE=1 fails to update hflags correctly and results in
hflags mismatch:
qemu: fatal: TCG hflags mismatch (current:0x2408003d rebuilt:0x240a003d)
This can be reproduced by running perf on a recent machine.
Some of the fragility here is the duplication of PMU hflags calculations.
This change consolidates that in a single place to update pmu-related
hflags, to be called after a well defined state changes.
The post-load PMU update is pulled out of the MSR update because it does
not depend on the MSR value.
Fixes: 8b3d1c49a9 ("target/ppc: Add new PMC HFLAGS")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230530130447.372617-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
28 lines
663 B
C
28 lines
663 B
C
/*
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* PMU emulation helpers for TCG IBM POWER chips
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef POWER8_PMU_H
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#define POWER8_PMU_H
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
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void cpu_ppc_pmu_init(CPUPPCState *env);
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void pmu_mmcr01_updated(CPUPPCState *env);
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#else
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static inline void cpu_ppc_pmu_init(CPUPPCState *env) { }
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static inline void pmu_mmcr01_updated(CPUPPCState *env) { }
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#endif
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#endif
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