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https://gitlab.com/qemu-project/qemu
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2b2f7d97d8
Add instructions of RLC opcode format. Add helper psw_write/read. Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
42 lines
1.6 KiB
C
42 lines
1.6 KiB
C
/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* Arithmetic */
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DEF_HELPER_3(add_ssov, i32, env, i32, i32)
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DEF_HELPER_3(add_suov, i32, env, i32, i32)
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DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
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DEF_HELPER_3(sub_suov, i32, env, i32, i32)
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DEF_HELPER_3(mul_ssov, i32, env, i32, i32)
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DEF_HELPER_3(mul_suov, i32, env, i32, i32)
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DEF_HELPER_3(sha_ssov, i32, env, i32, i32)
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DEF_HELPER_3(absdif_ssov, i32, env, i32, i32)
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/* CSA */
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DEF_HELPER_2(call, void, env, i32)
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DEF_HELPER_1(ret, void, env)
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DEF_HELPER_2(bisr, void, env, i32)
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DEF_HELPER_1(rfe, void, env)
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DEF_HELPER_2(ldlcx, void, env, i32)
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DEF_HELPER_2(lducx, void, env, i32)
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DEF_HELPER_2(stlcx, void, env, i32)
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DEF_HELPER_2(stucx, void, env, i32)
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/* Address mode helper */
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DEF_HELPER_1(br_update, i32, i32)
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DEF_HELPER_2(circ_update, i32, i32, i32)
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/* PSW cache helper */
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DEF_HELPER_2(psw_write, void, env, i32)
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DEF_HELPER_1(psw_read, i32, env)
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