qemu/target
Stefan Brankovic 8d745875c2 target/ppc: Fix for optimized vsl/vsr instructions
In previous implementation, invocation of TCG shift function could request
shift of TCG variable by 64 bits when variable 'sh' is 0, which is not
supported in TCG (values can be shifted by 0 to 63 bits). This patch fixes
this by using two separate invocation of TCG shift functions, with maximum
shift amount of 32.

Name of variable 'shifted' is changed to 'carry' so variable naming
is similar to old helper implementation.

Variables 'avrA' and 'avrB' are replaced with variable 'avr'.

Fixes: 4e6d0920e7
Reported-by: "Paul A. Clark" <pc@us.ibm.com>
Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Suggested-by: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
Signed-off-by: Stefan Brankovic <stefan.brankovic@rt-rk.com>
Message-Id: <1570196639-7025-2-git-send-email-stefan.brankovic@rt-rk.com>
Tested-by: Paul A. Clarke  <pc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-10-24 09:36:55 +11:00
..
alpha target/alpha: Tidy helper_fp_exc_raise_s 2019-09-26 19:00:53 +01:00
arm target/arm: Fix sign-extension for SMLAL* 2019-10-22 16:50:35 +01:00
cris Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
hppa target/hppa: prevent trashing of temporary in do_depw_sar() 2019-09-14 15:39:24 -04:00
i386 target/i386: Add Snowridge-v2 (no MPX) CPU model 2019-10-15 18:34:44 -03:00
lm32 Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
m68k target/m68k/fpu_helper.c: rename the access arguments 2019-09-19 12:12:19 +02:00
microblaze tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
mips target/mips: msa: Move helpers for <AND|NOR|OR|XOR>.V 2019-10-01 16:58:45 +02:00
moxie hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ 2019-08-21 13:24:01 +02:00
nios2 Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
openrisc target/openrisc: Update cpu "any" to v1.3 2019-09-04 13:01:56 -07:00
ppc target/ppc: Fix for optimized vsl/vsr instructions 2019-10-24 09:36:55 +11:00
riscv gdbstub: riscv: fix the fflags registers 2019-09-17 08:42:50 -07:00
s390x s390x/kvm: Set default cpu model for all machine classes 2019-10-21 18:03:08 +02:00
sh4 Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
sparc target/sparc: Switch to do_transaction_failed() hook 2019-09-17 12:01:00 +01:00
tilegx tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
tricore tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
unicore32 Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
xtensa target/xtensa: linux-user: add call0 ABI support 2019-09-11 08:47:06 +02:00