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103be64c26
Add PWCtl register (CP0 Register 5, Select 6). The PWCtl register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: PWEn (31) - Hardware Page Table walker enable PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only) XK (28) - If 1, walker handles xkseg (MIPS64 only) XS (27) - If 1, walker handles xsseg (MIPS64 only) XU (26) - If 1, walker handles xuseg (MIPS64 only) DPH (7) - Dual Page format of Huge Page support HugePg (6) - Huge Page PTE supported in Directory levels PSn (5..0) - Bit position of PTEvld in Huge Page PTE Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
318 lines
10 KiB
C
318 lines
10 KiB
C
#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "internal.h"
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#include "hw/hw.h"
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#include "migration/cpu.h"
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static int cpu_post_load(void *opaque, int version_id)
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{
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MIPSCPU *cpu = opaque;
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CPUMIPSState *env = &cpu->env;
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restore_fp_status(env);
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restore_msa_fp_status(env);
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compute_hflags(env);
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restore_pamask(env);
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return 0;
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}
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/* FPU state */
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static int get_fpr(QEMUFile *f, void *pv, size_t size, VMStateField *field)
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{
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int i;
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fpr_t *v = pv;
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/* Restore entire MSA vector register */
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for (i = 0; i < MSA_WRLEN/64; i++) {
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qemu_get_sbe64s(f, &v->wr.d[i]);
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}
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return 0;
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}
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static int put_fpr(QEMUFile *f, void *pv, size_t size, VMStateField *field,
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QJSON *vmdesc)
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{
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int i;
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fpr_t *v = pv;
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/* Save entire MSA vector register */
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for (i = 0; i < MSA_WRLEN/64; i++) {
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qemu_put_sbe64s(f, &v->wr.d[i]);
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}
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return 0;
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}
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const VMStateInfo vmstate_info_fpr = {
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.name = "fpr",
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.get = get_fpr,
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.put = put_fpr,
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};
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#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
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VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
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#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
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VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
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static VMStateField vmstate_fpu_fields[] = {
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VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
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VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
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VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
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VMSTATE_END_OF_LIST()
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};
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const VMStateDescription vmstate_fpu = {
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.name = "cpu/fpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = vmstate_fpu_fields
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};
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const VMStateDescription vmstate_inactive_fpu = {
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.name = "cpu/inactive_fpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = vmstate_fpu_fields
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};
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/* TC state */
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static VMStateField vmstate_tc_fields[] = {
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VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
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VMSTATE_UINTTL(PC, TCState),
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VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
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VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
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VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
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VMSTATE_UINTTL(DSPControl, TCState),
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VMSTATE_INT32(CP0_TCStatus, TCState),
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VMSTATE_INT32(CP0_TCBind, TCState),
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VMSTATE_UINTTL(CP0_TCHalt, TCState),
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VMSTATE_UINTTL(CP0_TCContext, TCState),
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VMSTATE_UINTTL(CP0_TCSchedule, TCState),
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VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
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VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
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VMSTATE_UINTTL(CP0_UserLocal, TCState),
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VMSTATE_INT32(msacsr, TCState),
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VMSTATE_END_OF_LIST()
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};
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const VMStateDescription vmstate_tc = {
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.name = "cpu/tc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = vmstate_tc_fields
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};
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const VMStateDescription vmstate_inactive_tc = {
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.name = "cpu/inactive_tc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = vmstate_tc_fields
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};
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/* MVP state */
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const VMStateDescription vmstate_mvp = {
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.name = "cpu/mvp",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
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VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
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VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
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VMSTATE_END_OF_LIST()
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}
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};
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/* TLB state */
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static int get_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field)
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{
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r4k_tlb_t *v = pv;
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uint16_t flags;
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qemu_get_betls(f, &v->VPN);
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qemu_get_be32s(f, &v->PageMask);
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qemu_get_be16s(f, &v->ASID);
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qemu_get_be16s(f, &flags);
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v->G = (flags >> 10) & 1;
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v->C0 = (flags >> 7) & 3;
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v->C1 = (flags >> 4) & 3;
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v->V0 = (flags >> 3) & 1;
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v->V1 = (flags >> 2) & 1;
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v->D0 = (flags >> 1) & 1;
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v->D1 = (flags >> 0) & 1;
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v->EHINV = (flags >> 15) & 1;
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v->RI1 = (flags >> 14) & 1;
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v->RI0 = (flags >> 13) & 1;
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v->XI1 = (flags >> 12) & 1;
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v->XI0 = (flags >> 11) & 1;
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qemu_get_be64s(f, &v->PFN[0]);
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qemu_get_be64s(f, &v->PFN[1]);
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return 0;
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}
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static int put_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field,
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QJSON *vmdesc)
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{
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r4k_tlb_t *v = pv;
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uint16_t asid = v->ASID;
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uint16_t flags = ((v->EHINV << 15) |
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(v->RI1 << 14) |
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(v->RI0 << 13) |
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(v->XI1 << 12) |
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(v->XI0 << 11) |
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(v->G << 10) |
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(v->C0 << 7) |
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(v->C1 << 4) |
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(v->V0 << 3) |
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(v->V1 << 2) |
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(v->D0 << 1) |
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(v->D1 << 0));
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qemu_put_betls(f, &v->VPN);
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qemu_put_be32s(f, &v->PageMask);
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qemu_put_be16s(f, &asid);
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qemu_put_be16s(f, &flags);
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qemu_put_be64s(f, &v->PFN[0]);
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qemu_put_be64s(f, &v->PFN[1]);
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return 0;
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}
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const VMStateInfo vmstate_info_tlb = {
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.name = "tlb_entry",
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.get = get_tlb,
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.put = put_tlb,
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};
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#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
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VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
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#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
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VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
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const VMStateDescription vmstate_tlb = {
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.name = "cpu/tlb",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
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VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
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VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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/* MIPS CPU state */
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const VMStateDescription vmstate_mips_cpu = {
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.name = "cpu",
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.version_id = 15,
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.minimum_version_id = 15,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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/* Active TC */
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VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
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/* Active FPU */
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VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
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CPUMIPSFPUContext),
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/* MVP */
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VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
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CPUMIPSMVPContext),
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/* TLB */
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VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
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CPUMIPSTLBContext),
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/* CPU metastate */
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VMSTATE_UINT32(env.current_tc, MIPSCPU),
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VMSTATE_UINT32(env.current_fpu, MIPSCPU),
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VMSTATE_INT32(env.error_code, MIPSCPU),
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VMSTATE_UINTTL(env.btarget, MIPSCPU),
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VMSTATE_UINTTL(env.bcond, MIPSCPU),
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/* Remaining CP0 registers */
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VMSTATE_INT32(env.CP0_Index, MIPSCPU),
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VMSTATE_INT32(env.CP0_Random, MIPSCPU),
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VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
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VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
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VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
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VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
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VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
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VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
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VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
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VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
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VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
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VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
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VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
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VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
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VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
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VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
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VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
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VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
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VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
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VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
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VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
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VMSTATE_INT32(env.CP0_Count, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
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VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
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VMSTATE_INT32(env.CP0_Status, MIPSCPU),
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VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
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VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
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VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
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VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
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VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
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VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
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VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
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VMSTATE_UINT64(env.lladdr, MIPSCPU),
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VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
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VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
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VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
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VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
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VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
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VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
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VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
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VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
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VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
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VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
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VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
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VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
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/* Inactive TC */
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VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
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vmstate_inactive_tc, TCState),
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VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
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vmstate_inactive_fpu, CPUMIPSFPUContext),
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VMSTATE_END_OF_LIST()
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},
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};
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