mirror of
https://gitlab.com/qemu-project/qemu
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134 lines
4 KiB
C
134 lines
4 KiB
C
/*
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* QEMU Bochs-style debug console ("port E9") emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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* Copyright (c) Intel Corporation; author: H. Peter Anvin
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h"
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#include "sysemu/char.h"
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#include "hw/isa/isa.h"
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#include "hw/i386/pc.h"
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#define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
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#define ISA_DEBUGCON_DEVICE(obj) \
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OBJECT_CHECK(ISADebugconState, (obj), TYPE_ISA_DEBUGCON_DEVICE)
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//#define DEBUG_DEBUGCON
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typedef struct DebugconState {
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MemoryRegion io;
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CharDriverState *chr;
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uint32_t readback;
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} DebugconState;
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typedef struct ISADebugconState {
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ISADevice parent_obj;
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uint32_t iobase;
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DebugconState state;
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} ISADebugconState;
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static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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DebugconState *s = opaque;
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unsigned char ch = val;
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#ifdef DEBUG_DEBUGCON
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printf("debugcon: write addr=0x%04x val=0x%02x\n", addr, val);
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#endif
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qemu_chr_fe_write(s->chr, &ch, 1);
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}
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static uint64_t debugcon_ioport_read(void *opaque, hwaddr addr, unsigned width)
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{
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DebugconState *s = opaque;
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#ifdef DEBUG_DEBUGCON
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printf("debugcon: read addr=0x%04x\n", addr);
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#endif
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return s->readback;
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}
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static const MemoryRegionOps debugcon_ops = {
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.read = debugcon_ioport_read,
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.write = debugcon_ioport_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 1,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void debugcon_init_core(DebugconState *s)
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{
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if (!s->chr) {
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fprintf(stderr, "Can't create debugcon device, empty char device\n");
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exit(1);
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}
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qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, s);
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}
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static int debugcon_isa_initfn(ISADevice *dev)
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{
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ISADebugconState *isa = ISA_DEBUGCON_DEVICE(dev);
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DebugconState *s = &isa->state;
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debugcon_init_core(s);
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memory_region_init_io(&s->io, &debugcon_ops, s,
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TYPE_ISA_DEBUGCON_DEVICE, 1);
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memory_region_add_subregion(isa_address_space_io(dev),
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isa->iobase, &s->io);
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return 0;
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}
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static Property debugcon_isa_properties[] = {
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DEFINE_PROP_HEX32("iobase", ISADebugconState, iobase, 0xe9),
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DEFINE_PROP_CHR("chardev", ISADebugconState, state.chr),
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DEFINE_PROP_HEX32("readback", ISADebugconState, state.readback, 0xe9),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
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ic->init = debugcon_isa_initfn;
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dc->props = debugcon_isa_properties;
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}
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static const TypeInfo debugcon_isa_info = {
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.name = TYPE_ISA_DEBUGCON_DEVICE,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(ISADebugconState),
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.class_init = debugcon_isa_class_initfn,
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};
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static void debugcon_register_types(void)
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{
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type_register_static(&debugcon_isa_info);
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}
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type_init(debugcon_register_types)
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