mirror of
https://gitlab.com/qemu-project/qemu
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353 lines
9.3 KiB
C
353 lines
9.3 KiB
C
/*
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* x86 FPREM test - executes the FPREM and FPREM1 instructions with corner case
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* operands and prints the operands, result and FPU status word.
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*
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* Run this on real hardware, then under QEMU, and diff the outputs, to compare
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* QEMU's implementation to your hardware. The 'run-test-i386-fprem' make
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* target does this.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2012 Catalin Patulea
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/compiler.h"
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#include "qemu/osdep.h"
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#include <stdio.h>
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#include <inttypes.h>
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/*
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* Inspired by <ieee754.h>'s union ieee854_long_double, but with single
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* long long mantissa fields and assuming little-endianness for simplicity.
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*/
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union float80u {
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long double d;
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/* This is the IEEE 854 double-extended-precision format. */
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struct {
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unsigned long long mantissa:63;
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unsigned int one:1;
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unsigned int exponent:15;
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unsigned int negative:1;
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unsigned int empty:16;
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} QEMU_PACKED ieee;
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/* This is for NaNs in the IEEE 854 double-extended-precision format. */
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struct {
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unsigned long long mantissa:62;
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unsigned int quiet_nan:1;
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unsigned int one:1;
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unsigned int exponent:15;
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unsigned int negative:1;
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unsigned int empty:16;
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} QEMU_PACKED ieee_nan;
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};
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#define IEEE854_LONG_DOUBLE_BIAS 0x3fff
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static const union float80u q_nan = {
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.ieee_nan.negative = 0, /* X */
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.ieee_nan.exponent = 0x7fff,
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.ieee_nan.one = 1,
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.ieee_nan.quiet_nan = 1,
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.ieee_nan.mantissa = 0,
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};
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static const union float80u s_nan = {
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.ieee_nan.negative = 0, /* X */
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.ieee_nan.exponent = 0x7fff,
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.ieee_nan.one = 1,
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.ieee_nan.quiet_nan = 0,
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.ieee_nan.mantissa = 1, /* nonzero */
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};
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static const union float80u pos_inf = {
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.ieee.negative = 0,
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.ieee.exponent = 0x7fff,
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.ieee.one = 1,
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.ieee.mantissa = 0,
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};
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static const union float80u pseudo_pos_inf = { /* "unsupported" */
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.ieee.negative = 0,
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.ieee.exponent = 0x7fff,
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.ieee.one = 0,
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.ieee.mantissa = 0,
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};
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static const union float80u pos_denorm = {
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.ieee.negative = 0,
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.ieee.exponent = 0,
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.ieee.one = 0,
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.ieee.mantissa = 1,
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};
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static const union float80u smallest_positive_norm = {
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.ieee.negative = 0,
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.ieee.exponent = 1,
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.ieee.one = 1,
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.ieee.mantissa = 0,
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};
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static void fninit()
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{
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asm volatile ("fninit\n");
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}
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static long double fprem(long double a, long double b, uint16_t *sw)
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{
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long double result;
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asm volatile ("fprem\n"
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"fnstsw %1\n"
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: "=t" (result), "=m" (*sw)
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: "0" (a), "u" (b)
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: "st(1)");
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return result;
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}
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static long double fprem1(long double a, long double b, uint16_t *sw)
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{
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long double result;
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asm volatile ("fprem1\n"
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"fnstsw %1\n"
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: "=t" (result), "=m" (*sw)
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: "0" (a), "u" (b)
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: "st(1)");
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return result;
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}
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#define FPUS_IE (1 << 0)
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#define FPUS_DE (1 << 1)
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#define FPUS_ZE (1 << 2)
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#define FPUS_OE (1 << 3)
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#define FPUS_UE (1 << 4)
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#define FPUS_PE (1 << 5)
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#define FPUS_SF (1 << 6)
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#define FPUS_SE (1 << 7)
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#define FPUS_C0 (1 << 8)
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#define FPUS_C1 (1 << 9)
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#define FPUS_C2 (1 << 10)
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#define FPUS_TOP 0x3800
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#define FPUS_C3 (1 << 14)
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#define FPUS_B (1 << 15)
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#define FPUS_EMASK 0x007f
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#define FPUC_EM 0x3f
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static void psw(uint16_t sw)
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{
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printf("SW: C3 TopC2C1C0\n");
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printf("SW: %c %d %3d %d %d %d %c %c %c %c %c %c %c %c\n",
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sw & FPUS_B ? 'B' : 'b',
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!!(sw & FPUS_C3),
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(sw & FPUS_TOP) >> 11,
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!!(sw & FPUS_C2),
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!!(sw & FPUS_C1),
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!!(sw & FPUS_C0),
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(sw & FPUS_SE) ? 'S' : 's',
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(sw & FPUS_SF) ? 'F' : 'f',
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(sw & FPUS_PE) ? 'P' : 'p',
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(sw & FPUS_UE) ? 'U' : 'u',
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(sw & FPUS_OE) ? 'O' : 'o',
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(sw & FPUS_ZE) ? 'Z' : 'z',
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(sw & FPUS_DE) ? 'D' : 'd',
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(sw & FPUS_IE) ? 'I' : 'i');
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}
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static void do_fprem(long double a, long double b)
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{
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const union float80u au = {.d = a};
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const union float80u bu = {.d = b};
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union float80u ru;
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uint16_t sw;
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printf("A: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
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au.ieee.negative, au.ieee.exponent, au.ieee.one,
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au.ieee_nan.quiet_nan, (unsigned long long)au.ieee.mantissa,
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a);
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printf("B: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
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bu.ieee.negative, bu.ieee.exponent, bu.ieee.one,
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bu.ieee_nan.quiet_nan, (unsigned long long)bu.ieee.mantissa,
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b);
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fflush(stdout);
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fninit();
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ru.d = fprem(a, b, &sw);
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psw(sw);
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printf("R : S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
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ru.ieee.negative, ru.ieee.exponent, ru.ieee.one,
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ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa,
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ru.d);
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fninit();
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ru.d = fprem1(a, b, &sw);
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psw(sw);
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printf("R1: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
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ru.ieee.negative, ru.ieee.exponent, ru.ieee.one,
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ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa,
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ru.d);
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printf("\n");
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}
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static void do_fprem_stack_underflow(void)
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{
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const long double a = 1.0;
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union float80u ru;
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uint16_t sw;
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fninit();
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asm volatile ("fprem\n"
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"fnstsw %1\n"
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: "=t" (ru.d), "=m" (sw)
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: "0" (a)
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: "st(1)");
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psw(sw);
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printf("R: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
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ru.ieee.negative, ru.ieee.exponent, ru.ieee.one,
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ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa,
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ru.d);
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printf("\n");
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}
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static void test_fprem_cases(void)
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{
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printf("= stack underflow =\n");
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do_fprem_stack_underflow();
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printf("= invalid operation =\n");
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do_fprem(s_nan.d, 1.0);
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do_fprem(1.0, 0.0);
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do_fprem(pos_inf.d, 1.0);
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do_fprem(pseudo_pos_inf.d, 1.0);
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printf("= denormal =\n");
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do_fprem(pos_denorm.d, 1.0);
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do_fprem(1.0, pos_denorm.d);
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/* printf("= underflow =\n"); */
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/* TODO: Is there a case where FPREM raises underflow? */
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}
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static void test_fprem_pairs(void)
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{
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unsigned long long count;
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unsigned int negative_index_a = 0;
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unsigned int negative_index_b = 0;
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static const unsigned int negative_values[] = {
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0,
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1,
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};
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unsigned int exponent_index_a = 0;
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unsigned int exponent_index_b = 0;
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static const unsigned int exponent_values[] = {
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0,
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1,
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2,
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IEEE854_LONG_DOUBLE_BIAS - 1,
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IEEE854_LONG_DOUBLE_BIAS,
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IEEE854_LONG_DOUBLE_BIAS + 1,
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0x7ffd,
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0x7ffe,
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0x7fff,
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};
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unsigned int one_index_a = 0;
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unsigned int one_index_b = 0;
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static const unsigned int one_values[] = {
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0,
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1,
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};
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unsigned int quiet_nan_index_a = 0;
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unsigned int quiet_nan_index_b = 0;
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static const unsigned int quiet_nan_values[] = {
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0,
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1,
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};
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unsigned int mantissa_index_a = 0;
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unsigned int mantissa_index_b = 0;
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static const unsigned long long mantissa_values[] = {
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0,
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1,
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2,
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0x3ffffffffffffffdULL,
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0x3ffffffffffffffeULL,
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0x3fffffffffffffffULL,
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};
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for (count = 0; ; ++count) {
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#define INIT_FIELD(var, field) \
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.ieee_nan.field = field##_values[field##_index_##var]
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const union float80u a = {
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INIT_FIELD(a, negative),
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INIT_FIELD(a, exponent),
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INIT_FIELD(a, one),
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INIT_FIELD(a, quiet_nan),
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INIT_FIELD(a, mantissa),
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};
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const union float80u b = {
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INIT_FIELD(b, negative),
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INIT_FIELD(b, exponent),
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INIT_FIELD(b, one),
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INIT_FIELD(b, quiet_nan),
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INIT_FIELD(b, mantissa),
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};
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#undef INIT_FIELD
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do_fprem(a.d, b.d);
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int carry = 1;
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#define CARRY_INTO(var, field) do { \
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if (carry) { \
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if (++field##_index_##var == ARRAY_SIZE(field##_values)) { \
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field##_index_##var = 0; \
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} else { \
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carry = 0; \
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} \
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} \
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} while (0)
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CARRY_INTO(b, mantissa);
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CARRY_INTO(b, quiet_nan);
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CARRY_INTO(b, one);
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CARRY_INTO(b, exponent);
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CARRY_INTO(b, negative);
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CARRY_INTO(a, mantissa);
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CARRY_INTO(a, quiet_nan);
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CARRY_INTO(a, one);
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CARRY_INTO(a, exponent);
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CARRY_INTO(a, negative);
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#undef CARRY_INTO
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if (carry) {
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break;
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}
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}
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fprintf(stderr, "test-i386-fprem: tested %llu cases\n", count);
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}
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int main(int argc, char **argv)
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{
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test_fprem_cases();
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test_fprem_pairs();
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return 0;
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}
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