Conor Dooley 1c8e491c45 target/riscv: support new isa extension detection devicetree properties ... A few months ago I submitted a patch to various lists, deprecating "riscv,isa" with a lengthy commit message [0] that is now commit aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux kernel tree. Primarily, the goal was to replace "riscv,isa" with a new set of properties that allowed for strictly defining the meaning of various extensions, where "riscv,isa" was tied to whatever definitions inflicted upon us by the ISA manual, which have seen some variance over time. Two new properties were introduced: "riscv,isa-base" and "riscv,isa-extensions". The former is a simple string to communicate the base ISA implemented by a hart and the latter an array of strings used to communicate the set of ISA extensions supported, per the definitions of each substring in extensions.yaml [1]. A beneficial side effect was also the ability to define vendor extensions in a more "official" way, as the ISA manual and other RVI specifications only covered the format for vendor extensions in the ISA string, but not the meaning of vendor extensions, for obvious reasons. Add support for setting these two new properties in the devicetrees for the various devicetree platforms supported by QEMU for RISC-V. The Linux kernel already supports parsing ISA extensions from these new properties, and documenting them in the dt-binding is a requirement for new extension detection being added to the kernel. A side effect of the implementation is that the meaning for elements in "riscv,isa" and in "riscv,isa-extensions" are now tied together as they are constructed from the same source. The same applies to the ISA string provided in ACPI tables, but there does not appear to be any strict definitions of meanings in ACPI land either. Link: https://lore.kernel.org/qemu-riscv/20230702-eats-scorebook-c951f170d29f@spud/ [0] Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/extensions.yaml [1] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240124-unvarying-foothold-9dde2aaf95d4@spud> [ Changes by AF: - Rebase on recent changes ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-02-09 20:43:14 +10:00
..
boot.c	target/riscv: Move misa_mxl_max to class	2024-02-09 20:43:14 +10:00
Kconfig	hw/riscv/virt-acpi-build.c: Add IO controllers and devices	2024-01-10 18:47:47 +10:00
meson.build	hw/riscv/virt: Enable basic ACPI infrastructure	2023-03-06 11:35:04 -08:00
microchip_pfsoc.c	hw/riscv: use qemu_configure_nic_device()	2024-02-02 16:23:47 +00:00
numa.c	hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()	2024-02-09 20:43:14 +10:00
opentitan.c	hw/riscv: opentitan: Fixup local variables shadowing	2023-09-29 10:07:20 +02:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv/shakti_c: Check CPU type in machine_run_board_init()	2024-01-05 16:20:15 +01:00
sifive_e.c	riscv: Fix SiFive E CLINT clock frequency	2023-11-22 13:57:19 +10:00
sifive_u.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
spike.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
virt-acpi-build.c	hw/riscv/virt-acpi-build.c: fix leak in build_rhct()	2024-02-09 20:43:14 +10:00
virt.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00