mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
7ee328804c
These functions are no longer used after making the generators object oriented. Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20231210220712.491494-10-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
1133 lines
38 KiB
Python
Executable file
1133 lines
38 KiB
Python
Executable file
#!/usr/bin/env python3
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##
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## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sys
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import re
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import string
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import textwrap
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behdict = {} # tag ->behavior
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semdict = {} # tag -> semantics
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attribdict = {} # tag -> attributes
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macros = {} # macro -> macro information...
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attribinfo = {} # Register information and misc
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registers = {} # register -> register functions
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new_registers = {}
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tags = [] # list of all tags
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overrides = {} # tags with helper overrides
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idef_parser_enabled = {} # tags enabled for idef-parser
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# We should do this as a hash for performance,
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# but to keep order let's keep it as a list.
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def uniquify(seq):
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seen = set()
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seen_add = seen.add
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return [x for x in seq if x not in seen and not seen_add(x)]
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regre = re.compile(r"((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)")
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immre = re.compile(r"[#]([rRsSuUm])(\d+)(?:[:](\d+))?")
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reg_or_immre = re.compile(
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r"(((?<!DUP)[MNRCOPQXSGVZA])([stuvwxyzdefg]+)"
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r"([.]?[LlHh]?)(\d+S?))|([#]([rRsSuUm])(\d+)[:]?(\d+)?)"
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)
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relimmre = re.compile(r"[#]([rR])(\d+)(?:[:](\d+))?")
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absimmre = re.compile(r"[#]([sSuUm])(\d+)(?:[:](\d+))?")
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finished_macros = set()
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def expand_macro_attribs(macro, allmac_re):
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if macro.key not in finished_macros:
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# Get a list of all things that might be macros
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l = allmac_re.findall(macro.beh)
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for submacro in l:
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if not submacro:
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continue
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if not macros[submacro]:
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raise Exception(f"Couldn't find macro: <{l}>")
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macro.attribs |= expand_macro_attribs(macros[submacro], allmac_re)
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finished_macros.add(macro.key)
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return macro.attribs
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# When qemu needs an attribute that isn't in the imported files,
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# we'll add it here.
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def add_qemu_macro_attrib(name, attrib):
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macros[name].attribs.add(attrib)
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immextre = re.compile(r"f(MUST_)?IMMEXT[(]([UuSsRr])")
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def is_cond_jump(tag):
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if tag == "J2_rte":
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return False
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if "A_HWLOOP0_END" in attribdict[tag] or "A_HWLOOP1_END" in attribdict[tag]:
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return False
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return re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) != None
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def is_cond_call(tag):
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return re.compile(r"(if.*fCALL)").search(semdict[tag]) != None
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def calculate_attribs():
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add_qemu_macro_attrib("fREAD_PC", "A_IMPLICIT_READS_PC")
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add_qemu_macro_attrib("fTRAP", "A_IMPLICIT_READS_PC")
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add_qemu_macro_attrib("fSET_OVERFLOW", "A_IMPLICIT_WRITES_USR")
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add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR")
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add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD")
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add_qemu_macro_attrib("fSTORE", "A_SCALAR_STORE")
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add_qemu_macro_attrib('fLSBNEW0', 'A_IMPLICIT_READS_P0')
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add_qemu_macro_attrib('fLSBNEW0NOT', 'A_IMPLICIT_READS_P0')
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add_qemu_macro_attrib('fREAD_P0', 'A_IMPLICIT_READS_P0')
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add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
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add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
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add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
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# Recurse down macros, find attributes from sub-macros
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macroValues = list(macros.values())
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allmacros_restr = "|".join(set([m.re.pattern for m in macroValues]))
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allmacros_re = re.compile(allmacros_restr)
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for macro in macroValues:
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expand_macro_attribs(macro, allmacros_re)
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# Append attributes to all instructions
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for tag in tags:
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for macname in allmacros_re.findall(semdict[tag]):
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if not macname:
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continue
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macro = macros[macname]
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attribdict[tag] |= set(macro.attribs)
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# Mark conditional jumps and calls
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# Not all instructions are properly marked with A_CONDEXEC
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for tag in tags:
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if is_cond_jump(tag) or is_cond_call(tag):
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attribdict[tag].add("A_CONDEXEC")
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def SEMANTICS(tag, beh, sem):
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# print tag,beh,sem
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behdict[tag] = beh
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semdict[tag] = sem
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attribdict[tag] = set()
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tags.append(tag) # dicts have no order, this is for order
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def ATTRIBUTES(tag, attribstring):
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attribstring = attribstring.replace("ATTRIBS", "").replace("(", "").replace(")", "")
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if not attribstring:
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return
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attribs = attribstring.split(",")
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for attrib in attribs:
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attribdict[tag].add(attrib.strip())
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class Macro(object):
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__slots__ = ["key", "name", "beh", "attribs", "re"]
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def __init__(self, name, beh, attribs):
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self.key = name
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self.name = name
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self.beh = beh
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self.attribs = set(attribs)
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self.re = re.compile("\\b" + name + "\\b")
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def MACROATTRIB(macname, beh, attribstring):
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attribstring = attribstring.replace("(", "").replace(")", "")
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if attribstring:
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attribs = attribstring.split(",")
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else:
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attribs = []
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macros[macname] = Macro(macname, beh, attribs)
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def compute_tag_regs(tag, full):
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tagregs = regre.findall(behdict[tag])
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if not full:
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tagregs = map(lambda reg: reg[:2], tagregs)
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return uniquify(tagregs)
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def compute_tag_immediates(tag):
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return uniquify(immre.findall(behdict[tag]))
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##
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## tagregs is the main data structure we'll use
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## tagregs[tag] will contain the registers used by an instruction
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## Within each entry, we'll use the regtype and regid fields
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## regtype can be one of the following
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## C control register
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## N new register value
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## P predicate register
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## R GPR register
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## M modifier register
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## Q HVX predicate vector
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## V HVX vector register
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## O HVX new vector register
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## regid can be one of the following
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## d, e destination register
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## dd destination register pair
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## s, t, u, v, w source register
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## ss, tt, uu, vv source register pair
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## x, y read-write register
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## xx, yy read-write register pair
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##
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def get_tagregs(full=False):
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compute_func = lambda tag: compute_tag_regs(tag, full)
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return dict(zip(tags, list(map(compute_func, tags))))
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def get_tagimms():
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return dict(zip(tags, list(map(compute_tag_immediates, tags))))
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def need_slot(tag):
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if (
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"A_CVI_SCATTER" not in attribdict[tag]
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and "A_CVI_GATHER" not in attribdict[tag]
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and ("A_STORE" in attribdict[tag]
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or "A_LOAD" in attribdict[tag])
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):
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return 1
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else:
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return 0
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def need_part1(tag):
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return re.compile(r"fPART1").search(semdict[tag])
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def need_ea(tag):
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return re.compile(r"\bEA\b").search(semdict[tag])
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def need_PC(tag):
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return "A_IMPLICIT_READS_PC" in attribdict[tag]
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def need_next_PC(tag):
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return "A_CALL" in attribdict[tag]
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def need_pkt_has_multi_cof(tag):
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return "A_COF" in attribdict[tag]
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def need_pkt_need_commit(tag):
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return 'A_IMPLICIT_WRITES_USR' in attribdict[tag]
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def skip_qemu_helper(tag):
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return tag in overrides.keys()
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def is_idef_parser_enabled(tag):
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return tag in idef_parser_enabled
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def imm_name(immlett):
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return f"{immlett}iV"
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def read_semantics_file(name):
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eval_line = ""
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for line in open(name, "rt").readlines():
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if not line.startswith("#"):
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eval_line += line
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if line.endswith("\\\n"):
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eval_line.rstrip("\\\n")
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else:
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eval(eval_line.strip())
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eval_line = ""
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def read_attribs_file(name):
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attribre = re.compile(
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r"DEF_ATTRIB\(([A-Za-z0-9_]+), ([^,]*), "
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+ r'"([A-Za-z0-9_\.]*)", "([A-Za-z0-9_\.]*)"\)'
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)
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for line in open(name, "rt").readlines():
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if not attribre.match(line):
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continue
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(attrib_base, descr, rreg, wreg) = attribre.findall(line)[0]
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attrib_base = "A_" + attrib_base
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attribinfo[attrib_base] = {"rreg": rreg, "wreg": wreg, "descr": descr}
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def read_overrides_file(name):
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overridere = re.compile(r"#define fGEN_TCG_([A-Za-z0-9_]+)\(.*")
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for line in open(name, "rt").readlines():
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if not overridere.match(line):
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continue
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tag = overridere.findall(line)[0]
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overrides[tag] = True
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def read_idef_parser_enabled_file(name):
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global idef_parser_enabled
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with open(name, "r") as idef_parser_enabled_file:
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lines = idef_parser_enabled_file.read().strip().split("\n")
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idef_parser_enabled = set(lines)
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def is_predicated(tag):
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return "A_CONDEXEC" in attribdict[tag]
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def code_fmt(txt):
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return textwrap.indent(textwrap.dedent(txt), " ")
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def hvx_newv(tag):
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if "A_CVI_NEW" in attribdict[tag]:
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return "EXT_NEW"
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elif "A_CVI_TMP" in attribdict[tag] or "A_CVI_TMP_DST" in attribdict[tag]:
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return "EXT_TMP"
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else:
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return "EXT_DFL"
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def vreg_offset_func(tag):
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if "A_CVI_TMP" in attribdict[tag] or "A_CVI_TMP_DST" in attribdict[tag]:
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return "ctx_tmp_vreg_off"
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else:
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return "ctx_future_vreg_off"
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class HelperArg:
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def __init__(self, proto_arg, call_arg, func_arg):
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self.proto_arg = proto_arg
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self.call_arg = call_arg
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self.func_arg = func_arg
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class Register:
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def __init__(self, regtype, regid):
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self.regtype = regtype
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self.regid = regid
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self.reg_num = f"{regtype}{regid}N"
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def decl_reg_num(self, f, regno):
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f.write(code_fmt(f"""\
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const int {self.reg_num} = insn->regno[{regno}];
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"""))
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def idef_arg(self, declared):
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declared.append(self.reg_tcg())
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def helper_arg(self):
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return HelperArg(
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self.helper_proto_type(),
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self.reg_tcg(),
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f"{self.helper_arg_type()} {self.helper_arg_name()}"
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)
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#
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# Every register is either Single or Pair or Hvx
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#
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class Scalar:
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def is_scalar_reg(self):
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return True
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def is_hvx_reg(self):
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return False
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def helper_arg_name(self):
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return self.reg_tcg()
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class Single(Scalar):
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def helper_proto_type(self):
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return "s32"
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def helper_arg_type(self):
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return "int32_t"
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class Pair(Scalar):
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def helper_proto_type(self):
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return "s64"
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def helper_arg_type(self):
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return "int64_t"
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class Hvx:
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def is_scalar_reg(self):
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return False
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def is_hvx_reg(self):
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return True
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def hvx_off(self):
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return f"{self.reg_tcg()}_off"
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def helper_proto_type(self):
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return "ptr"
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def helper_arg_type(self):
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return "void *"
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def helper_arg_name(self):
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return f"{self.reg_tcg()}_void"
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#
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# Every register is either Dest or OldSource or NewSource or ReadWrite
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#
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class Dest:
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def reg_tcg(self):
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return f"{self.regtype}{self.regid}V"
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def is_written(self):
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return True
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def is_writeonly(self):
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return True
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def is_read(self):
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return False
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def is_readwrite(self):
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return False
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class Source:
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def is_written(self):
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return False
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def is_writeonly(self):
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return False
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def is_read(self):
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return True
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def is_readwrite(self):
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return False
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class OldSource(Source):
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def reg_tcg(self):
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return f"{self.regtype}{self.regid}V"
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class NewSource(Source):
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def reg_tcg(self):
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return f"{self.regtype}{self.regid}N"
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class ReadWrite:
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def reg_tcg(self):
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return f"{self.regtype}{self.regid}V"
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def is_written(self):
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return True
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def is_writeonly(self):
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return False
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def is_read(self):
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return True
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def is_readwrite(self):
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return True
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class GprDest(Register, Single, Dest):
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def decl_tcg(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
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"""))
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def log_write(self, f, tag):
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f.write(code_fmt(f"""\
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gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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ctx_log_reg_write(ctx, {self.reg_num}, {predicated});
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"""))
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class GprSource(Register, Single, OldSource):
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def decl_tcg(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = hex_gpr[{self.reg_num}];
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_reg_read(ctx, {self.reg_num});
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"""))
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class GprNewSource(Register, Single, NewSource):
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def decl_tcg(self, f, tag, regno):
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = get_result_gpr(ctx, insn->regno[{regno}]);
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_reg_read(ctx, {self.reg_num});
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"""))
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class GprReadWrite(Register, Single, ReadWrite):
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def decl_tcg(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
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"""))
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## For read/write registers, we need to get the original value into
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## the result TCGv. For predicated instructions, this is done in
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## gen_start_packet. For un-predicated instructions, we do it here.
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if not is_predicated(tag):
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f.write(code_fmt(f"""\
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tcg_gen_mov_tl({self.reg_tcg()}, hex_gpr[{self.reg_num}]);
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"""))
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def log_write(self, f, tag):
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f.write(code_fmt(f"""\
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gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_write(ctx, {self.reg_num}, {predicated});
|
|
"""))
|
|
|
|
class ControlDest(Register, Single, Dest):
|
|
def decl_reg_num(self, f, regno):
|
|
f.write(code_fmt(f"""\
|
|
const int {self.reg_num} = insn->regno[{regno}] + HEX_REG_SA0;
|
|
"""))
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_write_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_write(ctx, {self.reg_num}, {predicated});
|
|
"""))
|
|
|
|
class ControlSource(Register, Single, OldSource):
|
|
def decl_reg_num(self, f, regno):
|
|
f.write(code_fmt(f"""\
|
|
const int {self.reg_num} = insn->regno[{regno}] + HEX_REG_SA0;
|
|
"""))
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno);
|
|
f.write(code_fmt(f"""\
|
|
TCGv {self.reg_tcg()} = tcg_temp_new();
|
|
gen_read_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_read(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class ModifierSource(Register, Single, OldSource):
|
|
def decl_reg_num(self, f, regno):
|
|
f.write(code_fmt(f"""\
|
|
const int {self.reg_num} = insn->regno[{regno}] + HEX_REG_M0;
|
|
"""))
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv {self.reg_tcg()} = hex_gpr[{self.reg_num}];
|
|
TCGv CS G_GNUC_UNUSED =
|
|
hex_gpr[{self.reg_num} - HEX_REG_M0 + HEX_REG_CS0];
|
|
"""))
|
|
def idef_arg(self, declared):
|
|
declared.append(self.reg_tcg())
|
|
declared.append("CS")
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_read(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class PredDest(Register, Single, Dest):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv {self.reg_tcg()} = tcg_temp_new();
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_pred_write(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class PredSource(Register, Single, OldSource):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv {self.reg_tcg()} = hex_pred[{self.reg_num}];
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_pred_read(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class PredNewSource(Register, Single, NewSource):
|
|
def decl_tcg(self, f, tag, regno):
|
|
f.write(code_fmt(f"""\
|
|
TCGv {self.reg_tcg()} = get_result_pred(ctx, insn->regno[{regno}]);
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_pred_read(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class PredReadWrite(Register, Single, ReadWrite):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv {self.reg_tcg()} = tcg_temp_new();
|
|
tcg_gen_mov_tl({self.reg_tcg()}, hex_pred[{self.reg_num}]);
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_pred_write(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class PairDest(Register, Pair, Dest):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv_i64 {self.reg_tcg()} =
|
|
get_result_gpr_pair(ctx, {self.reg_num});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated});
|
|
"""))
|
|
|
|
class PairSource(Register, Pair, OldSource):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
|
|
tcg_gen_concat_i32_i64({self.reg_tcg()},
|
|
hex_gpr[{self.reg_num}],
|
|
hex_gpr[{self.reg_num} + 1]);
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_read_pair(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class PairReadWrite(Register, Pair, ReadWrite):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv_i64 {self.reg_tcg()} =
|
|
get_result_gpr_pair(ctx, {self.reg_num});
|
|
tcg_gen_concat_i32_i64({self.reg_tcg()},
|
|
hex_gpr[{self.reg_num}],
|
|
hex_gpr[{self.reg_num} + 1]);
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated});
|
|
"""))
|
|
|
|
class ControlPairDest(Register, Pair, Dest):
|
|
def decl_reg_num(self, f, regno):
|
|
f.write(code_fmt(f"""\
|
|
const int {self.reg_num} = insn->regno[{regno}] + HEX_REG_SA0;
|
|
"""))
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv_i64 {self.reg_tcg()} =
|
|
get_result_gpr_pair(ctx, {self.reg_num});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_write_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated});
|
|
"""))
|
|
|
|
class ControlPairSource(Register, Pair, OldSource):
|
|
def decl_reg_num(self, f, regno):
|
|
f.write(code_fmt(f"""\
|
|
const int {self.reg_num} = insn->regno[{regno}] + HEX_REG_SA0;
|
|
"""))
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
|
|
gen_read_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_reg_read_pair(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class VRegDest(Register, Hvx, Dest):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
{vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, true);
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
pass
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
newv = hvx_newv(tag)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
|
|
"""))
|
|
|
|
class VRegSource(Register, Hvx, OldSource):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} = vreg_src_off(ctx, {self.reg_num});
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_read(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class VRegNewSource(Register, Hvx, NewSource):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
if skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
ctx_future_vreg_off(ctx, {self.reg_num}, 1, true);
|
|
"""))
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_read(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class VRegReadWrite(Register, Hvx, ReadWrite):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
{vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, true);
|
|
tcg_gen_gvec_mov(MO_64, {self.hvx_off()},
|
|
vreg_src_off(ctx, {self.reg_num}),
|
|
sizeof(MMVector), sizeof(MMVector));
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
pass
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
newv = hvx_newv(tag)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
|
|
"""))
|
|
|
|
class VRegTmp(Register, Hvx, ReadWrite):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} = offsetof(CPUHexagonState, vtmp);
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
tcg_gen_gvec_mov(MO_64, {self.hvx_off()},
|
|
vreg_src_off(ctx, {self.reg_num}),
|
|
sizeof(MMVector), sizeof(MMVector));
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_log_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},
|
|
{hvx_newv(tag)});
|
|
"""))
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
newv = hvx_newv(tag)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
|
|
"""))
|
|
|
|
class VRegPairDest(Register, Hvx, Dest):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
{vreg_offset_func(tag)}(ctx, {self.reg_num}, 2, true);
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
pass
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
newv = hvx_newv(tag)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated});
|
|
"""))
|
|
|
|
class VRegPairSource(Register, Hvx, OldSource):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
offsetof(CPUHexagonState, {self.reg_tcg()});
|
|
tcg_gen_gvec_mov(MO_64, {self.hvx_off()},
|
|
vreg_src_off(ctx, {self.reg_num}),
|
|
sizeof(MMVector), sizeof(MMVector));
|
|
tcg_gen_gvec_mov(MO_64, {self.hvx_off()} + sizeof(MMVector),
|
|
vreg_src_off(ctx, {self.reg_num} ^ 1),
|
|
sizeof(MMVector), sizeof(MMVector));
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_read_pair(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class VRegPairReadWrite(Register, Hvx, ReadWrite):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
offsetof(CPUHexagonState, {self.reg_tcg()});
|
|
tcg_gen_gvec_mov(MO_64, {self.hvx_off()},
|
|
vreg_src_off(ctx, {self.reg_num}),
|
|
sizeof(MMVector), sizeof(MMVector));
|
|
tcg_gen_gvec_mov(MO_64, {self.hvx_off()} + sizeof(MMVector),
|
|
vreg_src_off(ctx, {self.reg_num} ^ 1),
|
|
sizeof(MMVector), sizeof(MMVector));
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
f.write(code_fmt(f"""\
|
|
gen_log_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},
|
|
{hvx_newv(tag)});
|
|
"""))
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
newv = hvx_newv(tag)
|
|
predicated = "true" if is_predicated(tag) else "false"
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated});
|
|
"""))
|
|
|
|
class QRegDest(Register, Hvx, Dest):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
get_result_qreg(ctx, {self.reg_num});
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
pass
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_qreg_write(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class QRegSource(Register, Hvx, OldSource):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
offsetof(CPUHexagonState, QRegs[{self.reg_num}]);
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_read(self, f, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_qreg_read(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
class QRegReadWrite(Register, Hvx, ReadWrite):
|
|
def decl_tcg(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
const intptr_t {self.hvx_off()} =
|
|
get_result_qreg(ctx, {self.reg_num});
|
|
tcg_gen_gvec_mov(MO_64, {self.hvx_off()},
|
|
offsetof(CPUHexagonState, QRegs[{self.reg_num}]),
|
|
sizeof(MMQReg), sizeof(MMQReg));
|
|
"""))
|
|
if not skip_qemu_helper(tag):
|
|
f.write(code_fmt(f"""\
|
|
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
|
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
|
"""))
|
|
def log_write(self, f, tag):
|
|
pass
|
|
def helper_hvx_desc(self, f):
|
|
f.write(code_fmt(f"""\
|
|
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
|
"""))
|
|
def analyze_write(self, f, tag, regno):
|
|
self.decl_reg_num(f, regno)
|
|
f.write(code_fmt(f"""\
|
|
ctx_log_qreg_write(ctx, {self.reg_num});
|
|
"""))
|
|
|
|
def init_registers():
|
|
regs = {
|
|
GprDest("R", "d"),
|
|
GprDest("R", "e"),
|
|
GprSource("R", "s"),
|
|
GprSource("R", "t"),
|
|
GprSource("R", "u"),
|
|
GprSource("R", "v"),
|
|
GprReadWrite("R", "x"),
|
|
GprReadWrite("R", "y"),
|
|
ControlDest("C", "d"),
|
|
ControlSource("C", "s"),
|
|
ModifierSource("M", "u"),
|
|
PredDest("P", "d"),
|
|
PredDest("P", "e"),
|
|
PredSource("P", "s"),
|
|
PredSource("P", "t"),
|
|
PredSource("P", "u"),
|
|
PredSource("P", "v"),
|
|
PredReadWrite("P", "x"),
|
|
PairDest("R", "dd"),
|
|
PairDest("R", "ee"),
|
|
PairSource("R", "ss"),
|
|
PairSource("R", "tt"),
|
|
PairReadWrite("R", "xx"),
|
|
PairReadWrite("R", "yy"),
|
|
ControlPairDest("C", "dd"),
|
|
ControlPairSource("C", "ss"),
|
|
VRegDest("V", "d"),
|
|
VRegSource("V", "s"),
|
|
VRegSource("V", "u"),
|
|
VRegSource("V", "v"),
|
|
VRegSource("V", "w"),
|
|
VRegReadWrite("V", "x"),
|
|
VRegTmp("V", "y"),
|
|
VRegPairDest("V", "dd"),
|
|
VRegPairSource("V", "uu"),
|
|
VRegPairSource("V", "vv"),
|
|
VRegPairReadWrite("V", "xx"),
|
|
QRegDest("Q", "d"),
|
|
QRegDest("Q", "e"),
|
|
QRegSource("Q", "s"),
|
|
QRegSource("Q", "t"),
|
|
QRegSource("Q", "u"),
|
|
QRegSource("Q", "v"),
|
|
QRegReadWrite("Q", "x"),
|
|
}
|
|
for reg in regs:
|
|
registers[f"{reg.regtype}{reg.regid}"] = reg
|
|
|
|
new_regs = {
|
|
GprNewSource("N", "s"),
|
|
GprNewSource("N", "t"),
|
|
PredNewSource("P", "t"),
|
|
PredNewSource("P", "u"),
|
|
PredNewSource("P", "v"),
|
|
VRegNewSource("O", "s"),
|
|
}
|
|
for reg in new_regs:
|
|
new_registers[f"{reg.regtype}{reg.regid}"] = reg
|
|
|
|
def get_register(tag, regtype, regid):
|
|
if f"{regtype}{regid}V" in semdict[tag]:
|
|
return registers[f"{regtype}{regid}"]
|
|
else:
|
|
return new_registers[f"{regtype}{regid}"]
|
|
|
|
def helper_ret_type(tag, regs):
|
|
## If there is a scalar result, it is the return type
|
|
return_type = HelperArg( "void", "void", "void")
|
|
numscalarresults = 0
|
|
for regtype, regid in regs:
|
|
reg = get_register(tag, regtype, regid)
|
|
if reg.is_written() and reg.is_scalar_reg():
|
|
return_type = HelperArg(
|
|
reg.helper_proto_type(),
|
|
reg.reg_tcg(),
|
|
reg.helper_arg_type()
|
|
)
|
|
if numscalarresults > 1:
|
|
raise Exception("numscalarresults > 1")
|
|
return return_type
|
|
|
|
def helper_args(tag, regs, imms):
|
|
args = []
|
|
|
|
## First argument is the CPU state
|
|
args.append(HelperArg(
|
|
"env",
|
|
"tcg_env",
|
|
"CPUHexagonState *env"
|
|
))
|
|
|
|
## For predicated instructions, we pass in the destination register
|
|
if is_predicated(tag):
|
|
for regtype, regid in regs:
|
|
reg = get_register(tag, regtype, regid)
|
|
if reg.is_writeonly() and not reg.is_hvx_reg():
|
|
args.append(reg.helper_arg())
|
|
|
|
## Pass the HVX destination registers
|
|
for regtype, regid in regs:
|
|
reg = get_register(tag, regtype, regid)
|
|
if reg.is_written() and reg.is_hvx_reg():
|
|
args.append(reg.helper_arg())
|
|
|
|
## Pass the source registers
|
|
for regtype, regid in regs:
|
|
reg = get_register(tag, regtype, regid)
|
|
if reg.is_read() and not (reg.is_hvx_reg() and reg.is_readwrite()):
|
|
args.append(reg.helper_arg())
|
|
|
|
## Pass the immediates
|
|
for immlett, bits, immshift in imms:
|
|
args.append(HelperArg(
|
|
"s32",
|
|
f"tcg_constant_tl({imm_name(immlett)})",
|
|
f"int32_t {imm_name(immlett)}"
|
|
))
|
|
|
|
## Other stuff the helper might need
|
|
if need_pkt_has_multi_cof(tag):
|
|
args.append(HelperArg(
|
|
"i32",
|
|
"tcg_constant_tl(ctx->pkt->pkt_has_multi_cof)",
|
|
"uint32_t pkt_has_multi_cof"
|
|
))
|
|
if need_pkt_need_commit(tag):
|
|
args.append(HelperArg(
|
|
"i32",
|
|
"tcg_constant_tl(ctx->need_commit)",
|
|
"uint32_t pkt_need_commit"
|
|
))
|
|
if need_PC(tag):
|
|
args.append(HelperArg(
|
|
"i32",
|
|
"tcg_constant_tl(ctx->pkt->pc)",
|
|
"target_ulong PC"
|
|
))
|
|
if need_next_PC(tag):
|
|
args.append(HelperArg(
|
|
"i32",
|
|
"tcg_constant_tl(ctx->next_PC)",
|
|
"target_ulong next_PC"
|
|
))
|
|
if need_slot(tag):
|
|
args.append(HelperArg(
|
|
"i32",
|
|
"gen_slotval(ctx)",
|
|
"uint32_t slotval"
|
|
))
|
|
if need_part1(tag):
|
|
args.append(HelperArg(
|
|
"i32",
|
|
"tcg_constant_tl(insn->part1)"
|
|
"uint32_t part1"
|
|
))
|
|
return args
|