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This patch adds XVentanaCondOps support to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19 lines
379 B
C
19 lines
379 B
C
/*
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* QEMU disassembler -- RISC-V specific header (xventana*).
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*
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* Copyright (c) 2023 VRULL GmbH
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef DISAS_RISCV_XVENTANA_H
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#define DISAS_RISCV_XVENTANA_H
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#include "disas/riscv.h"
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extern const rv_opcode_data ventana_opcode_data[];
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void decode_xventanacondops(rv_decode*, rv_isa);
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#endif /* DISAS_RISCV_XVENTANA_H */
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