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61f3c91a67
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. This patch contains all the files, whose maintainer I could not get from ‘get_maintainer.pl’ script. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023124424.20177-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Adapted exec.c and qdev-monitor.c to new location] Signed-off-by: Thomas Huth <thuth@redhat.com>
197 lines
7 KiB
C
197 lines
7 KiB
C
/*
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* QEMU ICH Emulation
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*
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* Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
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* Copyright (c) 2010 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* lspci dump of a ICH-9 real device
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*
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* 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
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* Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
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* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
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* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
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* Latency: 0
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* Interrupt: pin B routed to IRQ 222
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* Region 0: I/O ports at d000 [size=8]
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* Region 1: I/O ports at cc00 [size=4]
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* Region 2: I/O ports at c880 [size=8]
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* Region 3: I/O ports at c800 [size=4]
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* Region 4: I/O ports at c480 [size=32]
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* Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
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* Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
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* Address: fee0f00c Data: 41d9
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* Capabilities: [70] Power Management version 3
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* Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
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* Status: D0 PME-Enable- DSel=0 DScale=0 PME-
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* Capabilities: [a8] SATA HBA <?>
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* Capabilities: [b0] Vendor Specific Information <?>
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* Kernel driver in use: ahci
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* Kernel modules: ahci
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* 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
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* 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
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* 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
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* 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
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* 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
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* 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
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* 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
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* 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
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* a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
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* b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
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* c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pci.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "hw/isa/isa.h"
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#include "sysemu/dma.h"
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#include "hw/ide/pci.h"
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#include "ahci_internal.h"
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#define ICH9_MSI_CAP_OFFSET 0x80
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#define ICH9_SATA_CAP_OFFSET 0xA8
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#define ICH9_IDP_BAR 4
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#define ICH9_MEM_BAR 5
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#define ICH9_IDP_INDEX 0x10
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#define ICH9_IDP_INDEX_LOG2 0x04
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static const VMStateDescription vmstate_ich9_ahci = {
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.name = "ich9_ahci",
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
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VMSTATE_AHCI(ahci, AHCIPCIState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void pci_ich9_reset(DeviceState *dev)
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{
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AHCIPCIState *d = ICH9_AHCI(dev);
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ahci_reset(&d->ahci);
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}
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static void pci_ich9_ahci_init(Object *obj)
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{
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struct AHCIPCIState *d = ICH9_AHCI(obj);
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ahci_init(&d->ahci, DEVICE(obj));
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}
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static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
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{
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struct AHCIPCIState *d;
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int sata_cap_offset;
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uint8_t *sata_cap;
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d = ICH9_AHCI(dev);
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int ret;
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ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
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pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
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dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
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dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
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pci_config_set_interrupt_pin(dev->config, 1);
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/* XXX Software should program this register */
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dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
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d->ahci.irq = pci_allocate_irq(dev);
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pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
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&d->ahci.idp);
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pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
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&d->ahci.mem);
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sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
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ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
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errp);
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if (sata_cap_offset < 0) {
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return;
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}
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sata_cap = dev->config + sata_cap_offset;
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pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
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pci_set_long(sata_cap + SATA_CAP_BAR,
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(ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
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d->ahci.idp_offset = ICH9_IDP_INDEX;
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/* Although the AHCI 1.3 specification states that the first capability
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* should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9
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* AHCI device puts the MSI capability first, pointing to 0x80. */
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ret = msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false, NULL);
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/* Any error other than -ENOTSUP(board's MSI support is broken)
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* is a programming error. Fall back to INTx silently on -ENOTSUP */
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assert(!ret || ret == -ENOTSUP);
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}
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static void pci_ich9_uninit(PCIDevice *dev)
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{
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struct AHCIPCIState *d;
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d = ICH9_AHCI(dev);
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msi_uninit(dev);
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ahci_uninit(&d->ahci);
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qemu_free_irq(d->ahci.irq);
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}
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static void ich_ahci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = pci_ich9_ahci_realize;
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k->exit = pci_ich9_uninit;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
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k->revision = 0x02;
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k->class_id = PCI_CLASS_STORAGE_SATA;
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dc->vmsd = &vmstate_ich9_ahci;
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dc->reset = pci_ich9_reset;
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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}
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static const TypeInfo ich_ahci_info = {
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.name = TYPE_ICH9_AHCI,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(AHCIPCIState),
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.instance_init = pci_ich9_ahci_init,
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.class_init = ich_ahci_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void ich_ahci_register_types(void)
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{
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type_register_static(&ich_ahci_info);
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}
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type_init(ich_ahci_register_types)
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