mirror of
https://gitlab.com/qemu-project/qemu
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03afdc28b3
Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.
Unfortunately we don't have much document about those instructions,
bit fields of CPUCFG instructions and IOCSR registers can be found
at 3A4000's user manual, while instruction encodings can be found
at arch/mips/include/asm/mach-loongson64/loongson_regs.h from
Linux Kernel.
Our predefined CPUCFG bits are differ from actual 3A4000, since
we can't emulate all CPUCFG features present in 3A4000 for now,
we just enable bits for what we have in TCG.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com>
[JY: Fixed typo in ase_lcsr_available(),
retrict GEN_FALSE_TRANS]
[PMD: Fix meson's mips_softmmu_ss -> mips_system_ss,
restrict AddressSpace/MemoryRegion to SysEmu]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
410 lines
13 KiB
C
410 lines
13 KiB
C
/*
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* MIPS internal definitions and helpers
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef MIPS_INTERNAL_H
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#define MIPS_INTERNAL_H
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#include "exec/memattrs.h"
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#ifdef CONFIG_TCG
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#include "tcg/tcg-internal.h"
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#endif
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#include "cpu.h"
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/*
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* MMU types, the first four entries have the same layout as the
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* CP0C0_MT field.
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*/
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enum mips_mmu_types {
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MMU_TYPE_NONE = 0,
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MMU_TYPE_R4000 = 1, /* Standard TLB */
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MMU_TYPE_BAT = 2, /* Block Address Translation */
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MMU_TYPE_FMT = 3, /* Fixed Mapping */
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MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */
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MMU_TYPE_R3000,
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MMU_TYPE_R6000,
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MMU_TYPE_R8000
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};
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struct mips_def_t {
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const char *name;
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int32_t CP0_PRid;
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int32_t CP0_Config0;
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int32_t CP0_Config1;
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int32_t CP0_Config2;
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int32_t CP0_Config3;
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int32_t CP0_Config4;
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int32_t CP0_Config4_rw_bitmask;
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int32_t CP0_Config5;
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int32_t CP0_Config5_rw_bitmask;
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int32_t CP0_Config6;
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int32_t CP0_Config6_rw_bitmask;
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int32_t CP0_Config7;
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int32_t CP0_Config7_rw_bitmask;
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target_ulong CP0_LLAddr_rw_bitmask;
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int CP0_LLAddr_shift;
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int32_t SYNCI_Step;
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/*
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* @CCRes: rate at which the coprocessor 0 counter increments
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*
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* The Count register acts as a timer, incrementing at a constant rate,
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* whether or not an instruction is executed, retired, or any forward
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* progress is made through the pipeline. The rate at which the counter
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* increments is implementation dependent, and is a function of the
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* pipeline clock of the processor, not the issue width of the processor.
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*/
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int32_t CCRes;
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int32_t CP0_Status_rw_bitmask;
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_SRSCtl;
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int32_t CP1_fcr0;
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int32_t CP1_fcr31_rw_bitmask;
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int32_t CP1_fcr31;
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int32_t MSAIR;
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int32_t SEGBITS;
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int32_t PABITS;
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int32_t CP0_SRSConf0_rw_bitmask;
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int32_t CP0_SRSConf0;
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int32_t CP0_SRSConf1_rw_bitmask;
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int32_t CP0_SRSConf1;
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int32_t CP0_SRSConf2_rw_bitmask;
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int32_t CP0_SRSConf2;
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int32_t CP0_SRSConf3_rw_bitmask;
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int32_t CP0_SRSConf3;
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int32_t CP0_SRSConf4_rw_bitmask;
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int32_t CP0_SRSConf4;
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int32_t CP0_PageGrain_rw_bitmask;
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int32_t CP0_PageGrain;
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target_ulong CP0_EBaseWG_rw_bitmask;
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uint32_t lcsr_cpucfg1;
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uint32_t lcsr_cpucfg2;
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uint64_t insn_flags;
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enum mips_mmu_types mmu_type;
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int32_t SAARP;
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};
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extern const char regnames[32][3];
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extern const char fregnames[32][4];
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extern const struct mips_def_t mips_defs[];
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extern const int mips_defs_number;
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int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
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#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
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#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
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#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
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#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
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#if !defined(CONFIG_USER_ONLY)
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enum {
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TLBRET_XI = -6,
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TLBRET_RI = -5,
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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};
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int get_physical_address(CPUMIPSState *env, hwaddr *physical,
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int *prot, target_ulong real_address,
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MMUAccessType access_type, int mmu_idx);
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hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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typedef struct r4k_tlb_t r4k_tlb_t;
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struct r4k_tlb_t {
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target_ulong VPN;
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uint32_t PageMask;
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uint16_t ASID;
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uint32_t MMID;
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unsigned int G:1;
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unsigned int C0:3;
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unsigned int C1:3;
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unsigned int V0:1;
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unsigned int V1:1;
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unsigned int D0:1;
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unsigned int D1:1;
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unsigned int XI0:1;
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unsigned int XI1:1;
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unsigned int RI0:1;
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unsigned int RI1:1;
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unsigned int EHINV:1;
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uint64_t PFN[2];
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};
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struct CPUMIPSTLBContext {
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uint32_t nb_tlb;
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uint32_t tlb_in_use;
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int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, MMUAccessType access_type);
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void (*helper_tlbwi)(CPUMIPSState *env);
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void (*helper_tlbwr)(CPUMIPSState *env);
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void (*helper_tlbp)(CPUMIPSState *env);
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void (*helper_tlbr)(CPUMIPSState *env);
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void (*helper_tlbinv)(CPUMIPSState *env);
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void (*helper_tlbinvf)(CPUMIPSState *env);
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union {
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struct {
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r4k_tlb_t tlb[MIPS_TLB_MAX];
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} r4k;
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} mmu;
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};
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
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extern const VMStateDescription vmstate_mips_cpu;
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#endif /* !CONFIG_USER_ONLY */
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static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
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{
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return (env->CP0_Status & (1 << CP0St_IE)) &&
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!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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/*
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* Note that the TCStatus IXMT field is initialized to zero,
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* and only MT capable cores can set it to one. So we don't
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* need to check for MT capabilities here.
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*/
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!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
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}
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/* Check if there is pending and not masked out interrupt */
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static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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{
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int32_t pending;
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int32_t status;
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bool r;
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pending = env->CP0_Cause & CP0Ca_IP_mask;
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status = env->CP0_Status & CP0Ca_IP_mask;
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if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
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/*
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* A MIPS configured with a vectorizing external interrupt controller
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* will feed a vector into the Cause pending lines. The core treats
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* the status lines as a vector level, not as individual masks.
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*/
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r = pending > status;
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} else {
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/*
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* A MIPS configured with compatibility or VInt (Vectored Interrupts)
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* treats the pending lines as individual interrupt lines, the status
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* lines are individual masks.
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*/
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r = (pending & status) != 0;
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}
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return r;
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}
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void msa_reset(CPUMIPSState *env);
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/* cp0_timer.c */
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uint32_t cpu_mips_get_count(CPUMIPSState *env);
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void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
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void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
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void cpu_mips_start_count(CPUMIPSState *env);
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void cpu_mips_stop_count(CPUMIPSState *env);
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static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
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{
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env->active_tc.PC = value & ~(target_ulong)1;
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if (value & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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} else {
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env->hflags &= ~(MIPS_HFLAG_M16);
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}
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}
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static inline void restore_pamask(CPUMIPSState *env)
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{
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if (env->hflags & MIPS_HFLAG_ELPA) {
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env->PAMask = (1ULL << env->PABITS) - 1;
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} else {
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env->PAMask = PAMASK_BASE;
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}
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}
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static inline int mips_vpe_active(CPUMIPSState *env)
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{
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int active = 1;
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/* Check that the VPE is enabled. */
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if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
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active = 0;
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}
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/* Check that the VPE is activated. */
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if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
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active = 0;
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}
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/*
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* Now verify that there are active thread contexts in the VPE.
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*
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* This assumes the CPU model will internally reschedule threads
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* if the active one goes to sleep. If there are no threads available
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* the active one will be in a sleeping state, and we can turn off
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* the entire VPE.
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*/
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if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
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/* TC is not activated. */
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active = 0;
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}
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if (env->active_tc.CP0_TCHalt & 1) {
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/* TC is in halt state. */
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active = 0;
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}
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return active;
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}
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static inline int mips_vp_active(CPUMIPSState *env)
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{
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CPUState *other_cs = first_cpu;
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/* Check if the VP disabled other VPs (which means the VP is enabled) */
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if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
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return 1;
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}
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/* Check if the virtual processor is disabled due to a DVP */
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CPU_FOREACH(other_cs) {
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MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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if ((&other_cpu->env != env) &&
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((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
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return 0;
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}
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}
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return 1;
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}
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static inline void compute_hflags(CPUMIPSState *env)
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{
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env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
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MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
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MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
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MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
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MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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env->hflags |= MIPS_HFLAG_ERL;
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}
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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env->hflags |= (env->CP0_Status >> CP0St_KSU) &
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MIPS_HFLAG_KSU;
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}
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#if defined(TARGET_MIPS64)
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if ((env->insn_flags & ISA_MIPS3) &&
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(((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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(env->CP0_Status & (1 << CP0St_PX)) ||
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(env->CP0_Status & (1 << CP0St_UX)))) {
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env->hflags |= MIPS_HFLAG_64;
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}
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if (!(env->insn_flags & ISA_MIPS3)) {
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env->hflags |= MIPS_HFLAG_AWRAP;
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} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
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!(env->CP0_Status & (1 << CP0St_UX))) {
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env->hflags |= MIPS_HFLAG_AWRAP;
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} else if (env->insn_flags & ISA_MIPS_R6) {
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/* Address wrapping for Supervisor and Kernel is specified in R6 */
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if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
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!(env->CP0_Status & (1 << CP0St_SX))) ||
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(((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
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!(env->CP0_Status & (1 << CP0St_KX)))) {
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env->hflags |= MIPS_HFLAG_AWRAP;
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}
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}
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#endif
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if (((env->CP0_Status & (1 << CP0St_CU0)) &&
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!(env->insn_flags & ISA_MIPS_R6)) ||
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!(env->hflags & MIPS_HFLAG_KSU)) {
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env->hflags |= MIPS_HFLAG_CP0;
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}
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if (env->CP0_Status & (1 << CP0St_CU1)) {
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env->hflags |= MIPS_HFLAG_FPU;
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}
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if (env->CP0_Status & (1 << CP0St_FR)) {
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env->hflags |= MIPS_HFLAG_F64;
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}
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if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
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(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
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env->hflags |= MIPS_HFLAG_SBRI;
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}
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if (env->insn_flags & ASE_DSP_R3) {
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/*
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* Our cpu supports DSP R3 ASE, so enable
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* access to DSP R3 resources.
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*/
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
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MIPS_HFLAG_DSP_R3;
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}
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} else if (env->insn_flags & ASE_DSP_R2) {
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/*
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* Our cpu supports DSP R2 ASE, so enable
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* access to DSP R2 resources.
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*/
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
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}
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} else if (env->insn_flags & ASE_DSP) {
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/*
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* Our cpu supports DSP ASE, so enable
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* access to DSP resources.
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*/
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP;
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}
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}
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if (env->insn_flags & ISA_MIPS_R2) {
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if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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} else if (env->insn_flags & ISA_MIPS_R1) {
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if (env->hflags & MIPS_HFLAG_64) {
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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} else if (env->insn_flags & ISA_MIPS4) {
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/*
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* All supported MIPS IV CPUs use the XX (CU3) to enable
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* and disable the MIPS IV extensions to the MIPS III ISA.
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* Some other MIPS IV CPUs ignore the bit, so the check here
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* would be too restrictive for them.
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*/
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if (env->CP0_Status & (1U << CP0St_CU3)) {
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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}
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if (ase_msa_available(env)) {
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if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
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env->hflags |= MIPS_HFLAG_MSA;
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}
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}
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
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env->hflags |= MIPS_HFLAG_FRE;
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}
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}
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if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
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if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
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env->hflags |= MIPS_HFLAG_ELPA;
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}
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}
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}
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#endif
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