mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
4d3203fd0b
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
250 lines
9.6 KiB
C
250 lines
9.6 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* DEF(name, oargs, iargs, cargs, flags)
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*/
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/* predefined ops */
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DEF(end, 0, 0, 0, 0) /* must be kept first */
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DEF(nop, 0, 0, 0, 0)
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DEF(nop1, 0, 0, 1, 0)
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DEF(nop2, 0, 0, 2, 0)
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DEF(nop3, 0, 0, 3, 0)
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DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
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DEF(discard, 1, 0, 0, 0)
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DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
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DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
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DEF(br, 0, 0, 1, TCG_OPF_BB_END)
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#define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
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#if TCG_TARGET_REG_BITS == 32
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# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
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#else
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# define IMPL64 TCG_OPF_64BIT
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#endif
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DEF(mov_i32, 1, 1, 0, 0)
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DEF(movi_i32, 1, 0, 1, 0)
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DEF(setcond_i32, 1, 2, 1, 0)
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DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
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/* load/store */
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DEF(ld8u_i32, 1, 1, 1, 0)
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DEF(ld8s_i32, 1, 1, 1, 0)
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DEF(ld16u_i32, 1, 1, 1, 0)
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DEF(ld16s_i32, 1, 1, 1, 0)
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DEF(ld_i32, 1, 1, 1, 0)
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DEF(st8_i32, 0, 2, 1, 0)
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DEF(st16_i32, 0, 2, 1, 0)
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DEF(st_i32, 0, 2, 1, 0)
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/* arith */
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DEF(add_i32, 1, 2, 0, 0)
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DEF(sub_i32, 1, 2, 0, 0)
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DEF(mul_i32, 1, 2, 0, 0)
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DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
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DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
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DEF(and_i32, 1, 2, 0, 0)
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DEF(or_i32, 1, 2, 0, 0)
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DEF(xor_i32, 1, 2, 0, 0)
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/* shifts/rotates */
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DEF(shl_i32, 1, 2, 0, 0)
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DEF(shr_i32, 1, 2, 0, 0)
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DEF(sar_i32, 1, 2, 0, 0)
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DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
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DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
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DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
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DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
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DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
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DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
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DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
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DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
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DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
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DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
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DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
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DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
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DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
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DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
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DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
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DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
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DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
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DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
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DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
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DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
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DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
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DEF(mov_i64, 1, 1, 0, IMPL64)
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DEF(movi_i64, 1, 0, 1, IMPL64)
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DEF(setcond_i64, 1, 2, 1, IMPL64)
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DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
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/* load/store */
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DEF(ld8u_i64, 1, 1, 1, IMPL64)
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DEF(ld8s_i64, 1, 1, 1, IMPL64)
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DEF(ld16u_i64, 1, 1, 1, IMPL64)
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DEF(ld16s_i64, 1, 1, 1, IMPL64)
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DEF(ld32u_i64, 1, 1, 1, IMPL64)
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DEF(ld32s_i64, 1, 1, 1, IMPL64)
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DEF(ld_i64, 1, 1, 1, IMPL64)
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DEF(st8_i64, 0, 2, 1, IMPL64)
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DEF(st16_i64, 0, 2, 1, IMPL64)
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DEF(st32_i64, 0, 2, 1, IMPL64)
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DEF(st_i64, 0, 2, 1, IMPL64)
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/* arith */
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DEF(add_i64, 1, 2, 0, IMPL64)
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DEF(sub_i64, 1, 2, 0, IMPL64)
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DEF(mul_i64, 1, 2, 0, IMPL64)
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DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
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DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
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DEF(and_i64, 1, 2, 0, IMPL64)
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DEF(or_i64, 1, 2, 0, IMPL64)
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DEF(xor_i64, 1, 2, 0, IMPL64)
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/* shifts/rotates */
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DEF(shl_i64, 1, 2, 0, IMPL64)
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DEF(shr_i64, 1, 2, 0, IMPL64)
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DEF(sar_i64, 1, 2, 0, IMPL64)
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DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
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DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
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DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
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DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
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DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
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DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
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DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
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DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
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DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
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DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
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DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
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DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
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DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
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DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
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DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
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DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
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DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
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DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
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DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
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DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
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DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
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DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
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DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
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DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
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/* QEMU specific */
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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DEF(debug_insn_start, 0, 0, 2, 0)
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#else
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DEF(debug_insn_start, 0, 0, 1, 0)
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#endif
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DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
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DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
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/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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constants must be defined */
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#if TCG_TARGET_REG_BITS == 32
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#if TARGET_LONG_BITS == 32
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DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#if TARGET_LONG_BITS == 32
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DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif
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#else /* TCG_TARGET_REG_BITS == 32 */
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DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#endif /* TCG_TARGET_REG_BITS != 32 */
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#undef IMPL
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#undef IMPL64
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#undef DEF
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