qemu/include
Bin Meng 145b299139 hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
This adds the QSPI0 controller to the SoC, and connects an ISSI
25WP256 flash to it. The generation of corresponding device tree
source fragment is also added.

Since the direct memory-mapped mode is not supported by the SiFive
SPI model, the <reg> property does not populate the second group
which represents the memory mapped address of the SPI flash.

With this commit, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU 'sifive_u' out of the box. This allows users
to develop and test the recommended RISC-V boot flow with a real
world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to
L2LIM, then U-Boot SPL loads the payload from SPI flash that is
combined with OpenSBI fw_dynamic firmware and U-Boot proper.

Specify machine property `msel` to 6 to allow booting from the SPI
flash. U-Boot spl is directly loaded via `-bios`, and subsequent
payload is stored in the SPI flash image. Example command line:

$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \
    -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04 09:43:29 -05:00
..
authz Prefer 'on' | 'off' over 'yes' | 'no' for bool options 2021-01-29 17:07:53 +00:00
block block: add bdrv_co_delete_file_noerr 2021-02-15 15:10:14 +01:00
chardev chardev: do not use machine_init_done 2020-12-15 12:51:51 -05:00
crypto qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
disas Hexagon (disas) disassembler 2021-02-18 07:48:22 -08:00
exec accel/tcg: allow plugin instrumentation to be disable via cflags 2021-02-18 08:19:23 +00:00
fpu softfloat: Define comparison operations for bfloat16 2020-08-29 19:25:42 -07:00
hw hw/riscv: sifive_u: Add QSPI0 controller and connect a flash 2021-03-04 09:43:29 -05:00
io io: add qio_channel_readv_full_all_eof & qio_channel_readv_full_all helpers 2021-02-10 09:23:28 +00:00
libdecnumber
migration migration: introduce a delete_snapshot wrapper 2021-02-08 11:19:51 +00:00
monitor sev: add sev-inject-launch-secret 2020-12-10 17:33:17 -05:00
net net: checksum: Introduce fine control over checksum type 2021-01-25 17:04:56 +08:00
qapi qapi: Introduce QAPI_LIST_APPEND 2021-01-28 08:08:45 +01:00
qemu qemu/int128: Add int128_or 2021-02-18 07:48:22 -08:00
qom qom: Allow optional sugar props 2021-02-08 16:57:37 +11:00
scsi scsi: introduce scsi_sense_from_errno() 2021-02-25 14:14:32 +01:00
standard-headers m68k: import bootinfo headers from linux 2021-02-11 21:56:42 +01:00
sysemu replay: fix icount request when replaying clock access 2021-02-16 17:15:39 +01:00
tcg tcg: Restart code generation when we run out of temps 2021-01-24 08:03:27 -10:00
ui ui/console: Remove dpy_gl_ctx_get_current 2021-02-19 15:07:14 +01:00
user trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
elf.h Hexagon (include/elf.h) ELF machine definition 2021-02-18 07:48:22 -08:00
glib-compat.h glib-compat: add g_unix_get_passwd_entry_qemu() 2020-11-02 19:52:08 -06:00
qemu-common.h vl: extract softmmu/datadir.c 2020-12-10 12:15:18 -05:00
qemu-io.h
trace-tcg.h