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139d941e5a
The PL022 interrupt registers have bits allocated as: 0: ROR (receive overrun) 1: RT (receive timeout) 2: RX (receive FIFO half full or less) 3: TX (transmit FIFO half full or less) A cut and paste error meant we had the wrong value for the PL022_INT_RT constant. This bug doesn't affect device behaviour, because we don't implement the receive timeout feature and so never set that interrupt bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-20-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
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| .. | ||
| aspeed_smc.c | ||
| imx_spi.c | ||
| Makefile.objs | ||
| mss-spi.c | ||
| omap_spi.c | ||
| pl022.c | ||
| ssi.c | ||
| stm32f2xx_spi.c | ||
| xilinx_spi.c | ||
| xilinx_spips.c | ||