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![Aleksandar Markovic](/assets/img/avatar_default.png)
This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In floating-point calculations, there is a need for denoting undefined or unrepresentable values. This is achieved by defining certain floating-point numerical values to be NaNs (which stands for "not a number"). For additional reasons, virtually all modern floating-point unit implementations use two kinds of NaNs: quiet and signaling. The binary representations of these two kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally, the first bit of mantissa). Up to 2008, standards for floating-point did not specify all details about binary representation of NaNs. More specifically, the meaning of the bit that is used for distinguishing between signaling and quiet NaNs was not strictly prescribed. (IEEE 754-2008 was the first floating-point standard that defined that meaning clearly, see [1], p. 35) As a result, different platforms took different approaches, and that presented considerable challenge for multi-platform emulators like QEMU. Mips platform represents the most complex case among QEMU-supported platforms regarding signaling NaN bit. Up to the Release 6 of Mips architecture, "1" in signaling NaN bit denoted signaling NaN, which is opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of that, Mips architecture for SIMD (also known as MSA, or vector instructions) also specifies signaling bit in accordance to IEEE standard. MSA unit can be implemented with both pre-Release 6 and Release 6 main processor units. QEMU uses SoftFloat library to implement various floating-point-related instructions on all platforms. The current QEMU implementation allows for defining meaning of signaling NaN bit during build time, and is implemented via preprocessor macro called SNAN_BIT_IS_ONE. On the other hand, the change in this patch enables SoftFloat library to be configured in run-time. This configuration is meant to occur during CPU initialization, at the moment when it is definitely known what desired behavior for particular CPU (or any additional FPUs) is. The change is implemented so that it is consistent with existing implementation of similar cases. This means that structure float_status is used for passing the information about desired signaling NaN bit on each invocation of SoftFloat functions. The additional field in float_status is called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE. IMPORTANT: This change is not meant to create any change in emulator behavior or functionality on any platform. It just provides the means for SoftFloat library to be used in a more flexible way - in other words, it will just prepare SoftFloat library for usage related to Mips platform and its specifics regarding signaling bit meaning, which is done in some of subsequent patches from this series. Further break down of changes: 1) Added field snan_bit_is_one to the structure float_status, and correspondent setter function set_snan_bit_is_one(). 2) Constants <float16|float32|float64|floatx80|float128>_default_nan (used both internally and externally) converted to functions <float16|float32|float64|floatx80|float128>_default_nan(float_status*). This is necessary since they are dependent on signaling bit meaning. At the same time, for the sake of code cleanup and simplicity, constants <floatx80|float128>_default_nan_<low|high> (used only internally within SoftFloat library) are removed, as not needed. 3) Added a float_status* argument to SoftFloat library functions XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_), XXX_maybe_silence_nan(XXX a_). This argument must be present in order to enable correct invocation of new version of functions XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128> here) 4) Updated code for all platforms to reflect changes in SoftFloat library. This change is twofolds: it includes modifications of SoftFloat library functions invocations, and an addition of invocation of function set_snan_bit_is_one() during CPU initialization, with arguments that are appropriate for each particular platform. It was established that all platforms zero their main CPU data structures, so snan_bit_is_one(0) in appropriate places is not added, as it is not needed. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, August 29, 2008. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * cherry-picked 2 chunks from patch #2 to fix compilation warnings] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
334 lines
8.7 KiB
C
334 lines
8.7 KiB
C
/*
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* QEMU SuperH CPU
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*
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* Copyright (c) 2005 Samuel Tardieu
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "migration/vmstate.h"
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#include "exec/exec-all.h"
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static void superh_cpu_set_pc(CPUState *cs, vaddr value)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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cpu->env.pc = value;
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}
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static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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cpu->env.pc = tb->pc;
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cpu->env.flags = tb->flags;
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}
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static bool superh_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & CPU_INTERRUPT_HARD;
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}
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/* CPUClass::reset() */
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static void superh_cpu_reset(CPUState *s)
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{
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SuperHCPU *cpu = SUPERH_CPU(s);
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
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CPUSH4State *env = &cpu->env;
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scc->parent_reset(s);
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memset(env, 0, offsetof(CPUSH4State, id));
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tlb_flush(s, 1);
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env->pc = 0xA0000000;
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#if defined(CONFIG_USER_ONLY)
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env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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#else
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env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
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(1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
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env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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#endif
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set_default_nan_mode(1, &env->fp_status);
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set_snan_bit_is_one(1, &env->fp_status);
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}
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static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_mach_sh4;
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info->print_insn = print_insn_sh;
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}
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typedef struct SuperHCPUListState {
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fprintf_function cpu_fprintf;
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FILE *file;
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} SuperHCPUListState;
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/* Sort alphabetically by type name. */
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static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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return strcmp(name_a, name_b);
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}
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static void superh_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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SuperHCPUListState *s = user_data;
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(*s->cpu_fprintf)(s->file, "%s\n",
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scc->name);
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}
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void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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SuperHCPUListState s = {
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.cpu_fprintf = cpu_fprintf,
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.file = f,
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};
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GSList *list;
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list = object_class_get_list(TYPE_SUPERH_CPU, false);
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list = g_slist_sort(list, superh_cpu_list_compare);
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g_slist_foreach(list, superh_cpu_list_entry, &s);
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g_slist_free(list);
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}
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static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
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{
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const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
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const char *name = b;
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return strcasecmp(scc->name, name);
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}
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static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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GSList *list, *item;
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if (cpu_model == NULL) {
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return NULL;
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}
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if (strcasecmp(cpu_model, "any") == 0) {
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return object_class_by_name(TYPE_SH7750R_CPU);
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}
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oc = object_class_by_name(cpu_model);
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if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
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&& !object_class_is_abstract(oc)) {
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return oc;
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}
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oc = NULL;
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list = object_class_get_list(TYPE_SUPERH_CPU, false);
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item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
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if (item != NULL) {
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oc = item->data;
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}
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g_slist_free(list);
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return oc;
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}
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SuperHCPU *cpu_sh4_init(const char *cpu_model)
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{
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return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
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}
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static void sh7750r_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7750R;
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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static void sh7750r_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7750R";
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scc->pvr = 0x00050000;
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scc->prr = 0x00000100;
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scc->cvr = 0x00110000;
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}
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static const TypeInfo sh7750r_type_info = {
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.name = TYPE_SH7750R_CPU,
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.parent = TYPE_SUPERH_CPU,
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.class_init = sh7750r_class_init,
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.instance_init = sh7750r_cpu_initfn,
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};
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static void sh7751r_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7751R;
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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static void sh7751r_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7751R";
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scc->pvr = 0x04050005;
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scc->prr = 0x00000113;
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scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
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}
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static const TypeInfo sh7751r_type_info = {
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.name = TYPE_SH7751R_CPU,
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.parent = TYPE_SUPERH_CPU,
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.class_init = sh7751r_class_init,
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.instance_init = sh7751r_cpu_initfn,
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};
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static void sh7785_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7785;
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env->features = SH_FEATURE_SH4A;
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}
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static void sh7785_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7785";
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scc->pvr = 0x10300700;
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scc->prr = 0x00000200;
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scc->cvr = 0x71440211;
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}
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static const TypeInfo sh7785_type_info = {
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.name = TYPE_SH7785_CPU,
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.parent = TYPE_SUPERH_CPU,
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.class_init = sh7785_class_init,
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.instance_init = sh7785_cpu_initfn,
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};
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static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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scc->parent_realize(dev, errp);
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}
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static void superh_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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cs->env_ptr = env;
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cpu_exec_init(cs, &error_abort);
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env->movcal_backup_tail = &(env->movcal_backup);
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if (tcg_enabled()) {
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sh4_translate_init();
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}
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}
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static const VMStateDescription vmstate_sh_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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static void superh_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->parent_realize = dc->realize;
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dc->realize = superh_cpu_realizefn;
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scc->parent_reset = cc->reset;
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cc->reset = superh_cpu_reset;
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cc->class_by_name = superh_cpu_class_by_name;
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cc->has_work = superh_cpu_has_work;
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cc->do_interrupt = superh_cpu_do_interrupt;
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cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
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cc->dump_state = superh_cpu_dump_state;
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cc->set_pc = superh_cpu_set_pc;
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cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
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cc->gdb_read_register = superh_cpu_gdb_read_register;
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cc->gdb_write_register = superh_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
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#else
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cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
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#endif
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cc->disas_set_info = superh_cpu_disas_set_info;
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cc->gdb_num_core_regs = 59;
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dc->vmsd = &vmstate_sh_cpu;
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/*
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* Reason: superh_cpu_initfn() calls cpu_exec_init(), which saves
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* the object in cpus -> dangling pointer after final
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* object_unref().
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*/
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dc->cannot_destroy_with_object_finalize_yet = true;
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}
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static const TypeInfo superh_cpu_type_info = {
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.name = TYPE_SUPERH_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(SuperHCPU),
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.instance_init = superh_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(SuperHCPUClass),
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.class_init = superh_cpu_class_init,
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};
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static void superh_cpu_register_types(void)
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{
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type_register_static(&superh_cpu_type_info);
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type_register_static(&sh7750r_type_info);
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type_register_static(&sh7751r_type_info);
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type_register_static(&sh7785_type_info);
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}
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type_init(superh_cpu_register_types)
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