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https://gitlab.com/qemu-project/qemu
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0e0824a1a9
Performing this early means that we can merge more cases within the non-logging switch statement. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-34-richard.henderson@linaro.org>
275 lines
7.9 KiB
C
275 lines
7.9 KiB
C
/*
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* Altera Nios II helper routines.
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/host-utils.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "exec/log.h"
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#include "exec/helper-proto.h"
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#include "semihosting/semihost.h"
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static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break)
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{
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CPUNios2State *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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uint32_t old_status = env->ctrl[CR_STATUS];
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uint32_t new_status = old_status;
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if ((old_status & CR_STATUS_EH) == 0) {
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int r_ea = R_EA, cr_es = CR_ESTATUS;
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if (is_break) {
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r_ea = R_BA;
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cr_es = CR_BSTATUS;
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}
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env->ctrl[cr_es] = old_status;
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env->regs[r_ea] = env->pc + 4;
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if (cpu->mmu_present) {
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new_status |= CR_STATUS_EH;
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}
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}
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new_status &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->ctrl[CR_STATUS] = new_status;
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env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
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CR_EXCEPTION, CAUSE,
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cs->exception_index);
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env->pc = exception_addr;
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}
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static void do_iic_irq(Nios2CPU *cpu)
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{
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do_exception(cpu, cpu->exception_addr, false);
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}
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void nios2_cpu_do_interrupt(CPUState *cs)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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const char *name = NULL;
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switch (cs->exception_index) {
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case EXCP_IRQ:
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name = "interrupt";
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break;
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case EXCP_TLBD:
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if (env->ctrl[CR_STATUS] & CR_STATUS_EH) {
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name = "TLB MISS (double)";
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} else {
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name = "TLB MISS (fast)";
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}
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break;
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case EXCP_TLBR:
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case EXCP_TLBW:
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case EXCP_TLBX:
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name = "TLB PERM";
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break;
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case EXCP_SUPERA:
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case EXCP_SUPERD:
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name = "SUPERVISOR (address)";
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break;
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case EXCP_SUPERI:
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name = "SUPERVISOR (insn)";
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break;
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case EXCP_ILLEGAL:
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name = "ILLEGAL insn";
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break;
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case EXCP_TRAP:
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name = "TRAP insn";
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break;
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case EXCP_BREAK:
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name = "BREAK insn";
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break;
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case EXCP_SEMIHOST:
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name = "SEMIHOST insn";
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break;
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}
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if (name) {
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qemu_log("%s at pc=0x%08x\n", name, env->pc);
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} else {
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qemu_log("Unknown exception %d at pc=0x%08x\n",
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cs->exception_index, env->pc);
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}
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}
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switch (cs->exception_index) {
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case EXCP_IRQ:
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do_iic_irq(cpu);
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break;
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case EXCP_TLBD:
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if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
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env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
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env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
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do_exception(cpu, cpu->fast_tlb_miss_addr, false);
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} else {
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env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL;
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do_exception(cpu, cpu->exception_addr, false);
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}
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break;
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case EXCP_TLBR:
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case EXCP_TLBW:
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case EXCP_TLBX:
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if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
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env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
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}
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do_exception(cpu, cpu->exception_addr, false);
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break;
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case EXCP_SUPERA:
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case EXCP_SUPERI:
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case EXCP_SUPERD:
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case EXCP_ILLEGAL:
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case EXCP_TRAP:
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do_exception(cpu, cpu->exception_addr, false);
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break;
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case EXCP_BREAK:
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do_exception(cpu, cpu->exception_addr, true);
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break;
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case EXCP_SEMIHOST:
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env->pc += 4;
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do_nios2_semihosting(env);
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break;
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default:
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cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index);
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}
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}
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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target_ulong vaddr, paddr = 0;
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Nios2MMULookup lu;
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unsigned int hit;
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if (cpu->mmu_present && (addr < 0xC0000000)) {
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hit = mmu_translate(env, &lu, addr, 0, 0);
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if (hit) {
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vaddr = addr & TARGET_PAGE_MASK;
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paddr = lu.paddr + vaddr - lu.vaddr;
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} else {
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paddr = -1;
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qemu_log("cpu_get_phys_page debug MISS: %#" PRIx64 "\n", addr);
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}
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} else {
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paddr = addr & TARGET_PAGE_MASK;
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}
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return paddr;
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}
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void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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env->ctrl[CR_BADADDR] = addr;
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env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN);
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helper_raise_exception(env, EXCP_UNALIGN);
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}
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bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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unsigned int excp = EXCP_TLBD;
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target_ulong vaddr, paddr;
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Nios2MMULookup lu;
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unsigned int hit;
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if (!cpu->mmu_present) {
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/* No MMU */
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address &= TARGET_PAGE_MASK;
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tlb_set_page(cs, address, address, PAGE_BITS,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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if (MMU_SUPERVISOR_IDX == mmu_idx) {
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if (address >= 0xC0000000) {
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/* Kernel physical page - TLB bypassed */
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address &= TARGET_PAGE_MASK;
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tlb_set_page(cs, address, address, PAGE_BITS,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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} else {
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if (address >= 0x80000000) {
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/* Illegal access from user mode */
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if (probe) {
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return false;
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}
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cs->exception_index = EXCP_SUPERA;
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env->ctrl[CR_BADADDR] = address;
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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/* Virtual page. */
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hit = mmu_translate(env, &lu, address, access_type, mmu_idx);
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if (hit) {
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vaddr = address & TARGET_PAGE_MASK;
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paddr = lu.paddr + vaddr - lu.vaddr;
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if (((access_type == MMU_DATA_LOAD) && (lu.prot & PAGE_READ)) ||
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((access_type == MMU_DATA_STORE) && (lu.prot & PAGE_WRITE)) ||
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((access_type == MMU_INST_FETCH) && (lu.prot & PAGE_EXEC))) {
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tlb_set_page(cs, vaddr, paddr, lu.prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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/* Permission violation */
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excp = (access_type == MMU_DATA_LOAD ? EXCP_TLBR :
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access_type == MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX);
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}
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if (probe) {
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return false;
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}
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env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC, D,
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access_type != MMU_INST_FETCH);
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env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN,
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address >> TARGET_PAGE_BITS);
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env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR];
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cs->exception_index = excp;
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env->ctrl[CR_BADADDR] = address;
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cpu_loop_exit_restore(cs, retaddr);
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}
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