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dd673288a8
MP initialization protocol differs between cpu families, and for P6 and
onward models it is up to CPU to decide if it will be BSP using this
protocol, so try to model this. However there is no point in implementing
MP initialization protocol in qemu. Thus first CPU is always marked as BSP.
This patch:
- moves decision to designate BSP from board into cpu, making cpu
self-sufficient in this regard. Later it will allow to cleanup hw/pc.c
and remove cpu_reset and wrappers from there.
- stores flag that CPU is BSP in IA32_APIC_BASE to model behavior
described in Inted SDM vol 3a part 1 chapter 8.4.1
- uses MSR_IA32_APICBASE_BSP flag in apic_base for checking if cpu is BSP
patch is based on Jan Kiszka's proposal:
http://thread.gmane.org/gmane.comp.emulators.qemu/100806
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
32 lines
1 KiB
C
32 lines
1 KiB
C
#ifndef APIC_H
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#define APIC_H
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#include "qemu-common.h"
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/* apic.c */
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
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uint8_t vector_num, uint8_t trigger_mode);
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int apic_accept_pic_intr(DeviceState *s);
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void apic_deliver_pic_intr(DeviceState *s, int level);
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void apic_deliver_nmi(DeviceState *d);
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int apic_get_interrupt(DeviceState *s);
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void apic_reset_irq_delivered(void);
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int apic_get_irq_delivered(void);
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void cpu_set_apic_base(DeviceState *s, uint64_t val);
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uint64_t cpu_get_apic_base(DeviceState *s);
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void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
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uint8_t cpu_get_apic_tpr(DeviceState *s);
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void apic_init_reset(DeviceState *s);
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void apic_sipi(DeviceState *s);
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void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
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TPRAccess access);
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void apic_poll_irq(DeviceState *d);
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void apic_designate_bsp(DeviceState *d);
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/* pc.c */
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DeviceState *cpu_get_current_apic(void);
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/* cpu.c */
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bool cpu_is_bsp(X86CPU *cpu);
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#endif
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