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To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-6-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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boot.h | ||
boot_opensbi.h | ||
microchip_pfsoc.h | ||
numa.h | ||
opentitan.h | ||
riscv_hart.h | ||
shakti_c.h | ||
sifive_cpu.h | ||
sifive_e.h | ||
sifive_u.h | ||
spike.h | ||
virt.h |