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https://gitlab.com/qemu-project/qemu
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e3205306d8
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
32 lines
735 B
C
32 lines
735 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define LoongArch target-specific constraint sets.
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*
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* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
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*
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* Based on tcg/riscv/tcg-target-con-set.h
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*
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(rZ, r)
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C_O0_I2(rZ, rZ)
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C_O1_I1(r, r)
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C_O1_I2(r, r, rC)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, r, rI)
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C_O1_I2(r, r, rJ)
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C_O1_I2(r, r, rU)
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C_O1_I2(r, r, rW)
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C_O1_I2(r, r, rZ)
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C_O1_I2(r, 0, rZ)
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C_O1_I2(r, rZ, ri)
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C_O1_I2(r, rZ, rJ)
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C_O1_I2(r, rZ, rZ)
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C_O1_I4(r, rZ, rJ, rZ, rZ)
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