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Fix typos in comments (interupt -> interrupt)

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Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
This commit is contained in:
Stefan Weil 2011-04-28 17:20:35 +02:00 committed by Stefan Hajnoczi
parent 0cf818c476
commit ff2712ba89
5 changed files with 6 additions and 6 deletions
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2
cpu-exec.c
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@ -569,7 +569,7 @@ int cpu_exec(CPUState *env1)
next_tb = 0; next_tb = 0;
} }
#endif #endif
/* Don't use the cached interupt_request value, /* Don't use the cached interrupt_request value,
do_interrupt may have updated the EXITTB flag. */ do_interrupt may have updated the EXITTB flag. */
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;

2
hw/mst_fpga.c
View file

@ -154,7 +154,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
case MST_MSCRD: case MST_MSCRD:
s->mscrd = value; s->mscrd = value;
break; break;
case MST_INTMSKENA: /* Mask interupt */ case MST_INTMSKENA: /* Mask interrupt */
s->intmskena = (value & 0xFEEFF); s->intmskena = (value & 0xFEEFF);
qemu_set_irq(s->parent, s->intsetclr & s->intmskena); qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
break; break;

2
hw/pl031.c
View file

@ -161,7 +161,7 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
pl031_update(s); pl031_update(s);
break; break;
case RTC_ICR: case RTC_ICR:
/* The PL031 documentation (DDI0224B) states that the interupt is /* The PL031 documentation (DDI0224B) states that the interrupt is
cleared when bit 0 of the written value is set. However the cleared when bit 0 of the written value is set. However the
arm926e documentation (DDI0287B) states that the interrupt is arm926e documentation (DDI0287B) states that the interrupt is
cleared when any value is written. */ cleared when any value is written. */

4
hw/pl061.c
View file

@ -98,7 +98,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
return s->isense; return s->isense;
case 0x408: /* Interrupt both edges */ case 0x408: /* Interrupt both edges */
return s->ibe; return s->ibe;
case 0x40c: /* Interupt event */ case 0x40c: /* Interrupt event */
return s->iev; return s->iev;
case 0x410: /* Interrupt mask */ case 0x410: /* Interrupt mask */
return s->im; return s->im;
@ -156,7 +156,7 @@ static void pl061_write(void *opaque, target_phys_addr_t offset,
case 0x408: /* Interrupt both edges */ case 0x408: /* Interrupt both edges */
s->ibe = value; s->ibe = value;
break; break;
case 0x40c: /* Interupt event */ case 0x40c: /* Interrupt event */
s->iev = value; s->iev = value;
break; break;
case 0x410: /* Interrupt mask */ case 0x410: /* Interrupt mask */

2
target-mips/translate_init.c
View file

@ -38,7 +38,7 @@
((1 << CP0C2_M)) ((1 << CP0C2_M))
/* No config4, no DSP ASE, no large physaddr (PABITS), /* No config4, no DSP ASE, no large physaddr (PABITS),
no external interrupt controller, no vectored interupts, no external interrupt controller, no vectored interrupts,
no 1kb pages, no SmartMIPS ASE, no trace logic */ no 1kb pages, no SmartMIPS ASE, no trace logic */
#define MIPS_CONFIG3 \ #define MIPS_CONFIG3 \
((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \