mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
target/riscv: enable riscv kvm accel
Add riscv kvm support in meson.build file. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Message-id: 20220112081329.1835-14-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
1eb9a5da31
commit
fbf43c7dbf
1 changed files with 2 additions and 0 deletions
|
@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
|
|||
kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
|
||||
elif cpu in ['mips', 'mips64']
|
||||
kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
|
||||
elif cpu in ['riscv']
|
||||
kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
|
||||
else
|
||||
kvm_targets = []
|
||||
endif
|
||||
|
|
Loading…
Reference in a new issue