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target/sparc: Implement FSLL, FSRL, FSRA, FSLAS

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 17:24:01 -07:00
parent 669e077437
commit fbc5c8d4e8
4 changed files with 58 additions and 0 deletions
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2
target/sparc/helper.h
View file

@ -119,6 +119,8 @@ DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmean16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fslas16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fslas32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \

9
target/sparc/insns.decode
View file

@ -408,6 +408,15 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d
FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d
FSLL16 10 ..... 110110 ..... 0 0010 0001 ..... @d_d_d
FSRL16 10 ..... 110110 ..... 0 0010 0011 ..... @d_d_d
FSLAS16 10 ..... 110110 ..... 0 0010 1001 ..... @d_d_d
FSRA16 10 ..... 110110 ..... 0 0010 1011 ..... @d_d_d
FSLL32 10 ..... 110110 ..... 0 0010 0101 ..... @d_d_d
FSRL32 10 ..... 110110 ..... 0 0010 0111 ..... @d_d_d
FSLAS32 10 ..... 110110 ..... 0 0010 1101 ..... @d_d_d
FSRA32 10 ..... 110110 ..... 0 0010 1111 ..... @d_d_d
FPCMPULE8 10 ..... 110110 ..... 1 0010 0000 ..... @r_d_d
FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d
FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d

11
target/sparc/translate.c
View file

@ -83,6 +83,8 @@
# define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fslas16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fslas32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fstox ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL; })
@ -4961,6 +4963,13 @@ TRANS(FPADDS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_ssadd)
TRANS(FPSUBS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sssub)
TRANS(FPSUBS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sssub)
TRANS(FSLL16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_shlv)
TRANS(FSLL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shlv)
TRANS(FSRL16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_shrv)
TRANS(FSRL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shrv)
TRANS(FSRA16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sarv)
TRANS(FSRA32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sarv)
static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
{
@ -5000,6 +5009,8 @@ TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd)
TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64)
TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64)
TRANS(FSLAS16, VIS3, do_ddd, a, gen_helper_fslas16)
TRANS(FSLAS32, VIS3, do_ddd, a, gen_helper_fslas32)
static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv, TCGv_i64, TCGv_i64))

36
target/sparc/vis_helper.c
View file

@ -473,3 +473,39 @@ uint64_t helper_fmean16(uint64_t src1, uint64_t src2)
return r.ll;
}
uint64_t helper_fslas16(uint64_t src1, uint64_t src2)
{
VIS64 r, s1, s2;
s1.ll = src1;
s2.ll = src2;
r.ll = 0;
for (int i = 0; i < 4; ++i) {
int t = s1.VIS_SW64(i) << (s2.VIS_W64(i) % 16);
t = MIN(t, INT16_MAX);
t = MAX(t, INT16_MIN);
r.VIS_SW64(i) = t;
}
return r.ll;
}
uint64_t helper_fslas32(uint64_t src1, uint64_t src2)
{
VIS64 r, s1, s2;
s1.ll = src1;
s2.ll = src2;
r.ll = 0;
for (int i = 0; i < 2; ++i) {
int64_t t = (int64_t)(int32_t)s1.VIS_L64(i) << (s2.VIS_L64(i) % 32);
t = MIN(t, INT32_MAX);
t = MAX(t, INT32_MIN);
r.VIS_L64(i) = t;
}
return r.ll;
}