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tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So let's make each register unique. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -11,6 +11,7 @@ TESTS += test_fadd.tst
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TESTS += test_fmul.tst
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TESTS += test_ftoi.tst
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TESTS += test_imask.tst
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TESTS += test_insert.tst
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TESTS += test_madd.tst
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TESTS += test_msub.tst
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TESTS += test_muls.tst
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@ -9,10 +9,10 @@
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/* Register definitions */
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#define DREG_RS1 %d0
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#define DREG_RS2 %d1
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#define DREG_RS3 %d4
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#define DREG_CALC_RESULT %d1
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#define DREG_CALC_PSW %d2
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#define DREG_CORRECT_PSW %d3
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#define DREG_RS3 %d2
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#define DREG_CALC_RESULT %d3
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#define DREG_CALC_PSW %d4
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#define DREG_CORRECT_PSW %d5
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#define DREG_TEMP_LI %d10
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#define DREG_TEMP %d11
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#define DREG_TEST_NUM %d14
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@ -103,6 +103,14 @@ test_ ## num: \
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insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
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)
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#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
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TEST_CASE(num, DREG_CALC_RESULT, result, \
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LI(DREG_RS1, rs1); \
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LI(DREG_RS2, rs1); \
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rstv; \
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insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
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)
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#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
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TEST_CASE_E(num, res_lo, res_hi, \
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LI(EREG_RS1_LO, rs1_lo); \
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9
tests/tcg/tricore/test_insert.S
Normal file
9
tests/tcg/tricore/test_insert.S
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@ -0,0 +1,9 @@
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#include "macros.h"
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.text
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.global _start
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_start:
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# insn num result rs1 imm1 rs2 imm2
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# | | | | | | |
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TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
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TEST_PASSFAIL
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