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target/xtensa: implement FPU division and square root

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This does not implement all opcodes related to div/sqrt as specified in
the xtensa ISA, partly because the official specification is not
complete and partly because precise implementation is unnecessarily
complex. Instead instructions specific to the div/sqrt sequences are
implemented differently, most of them as nops, but the results of
div/sqrt sequences is preserved.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2020-03-14 11:13:53 -07:00
parent cfa9f05181
commit f8c6137016
3 changed files with 132 additions and 0 deletions
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24
target/xtensa/fpu_helper.c
View File

@ -231,6 +231,30 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
&env->fp_status);
}
float64 HELPER(mkdadj_d)(CPUXtensaState *env, float64 a, float64 b)
{
set_use_first_nan(true, &env->fp_status);
return float64_div(b, a, &env->fp_status);
}
float32 HELPER(mkdadj_s)(CPUXtensaState *env, float32 a, float32 b)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_div(b, a, &env->fp_status);
}
float64 HELPER(mksadj_d)(CPUXtensaState *env, float64 v)
{
set_use_first_nan(true, &env->fp_status);
return float64_sqrt(v, &env->fp_status);
}
float32 HELPER(mksadj_s)(CPUXtensaState *env, float32 v)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_sqrt(v, &env->fp_status);
}
uint32_t HELPER(ftoi_d)(CPUXtensaState *env, float64 v,
uint32_t rounding_mode, uint32_t scale)
{

4
target/xtensa/helper.h
View File

@ -83,6 +83,10 @@ DEF_HELPER_4(madd_d, f64, env, f64, f64, f64)
DEF_HELPER_4(madd_s, f32, env, f32, f32, f32)
DEF_HELPER_4(msub_d, f64, env, f64, f64, f64)
DEF_HELPER_4(msub_s, f32, env, f32, f32, f32)
DEF_HELPER_3(mkdadj_d, f64, env, f64, f64)
DEF_HELPER_3(mkdadj_s, f32, env, f32, f32)
DEF_HELPER_2(mksadj_d, f64, env, f64)
DEF_HELPER_2(mksadj_s, f32, env, f32)
DEF_HELPER_4(ftoi_d, i32, env, f64, i32, i32)
DEF_HELPER_4(ftoui_d, i32, env, f64, i32, i32)
DEF_HELPER_3(itof_d, f64, env, i32, i32)

104
target/xtensa/translate.c
View File

@ -7314,6 +7314,38 @@ static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
}
}
static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in);
}
static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
OpcodeArg arg32[2];
get_f32_o1_i2(arg, arg32, 0, 0, 1);
gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in);
put_f32_o1_i2(arg, arg32, 0, 0, 1);
}
static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in);
}
static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
OpcodeArg arg32[2];
get_f32_o1_i1(arg, arg32, 0, 1);
gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in);
put_f32_o1_i1(arg, arg32, 0, 1);
}
static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@ -7349,6 +7381,22 @@ static const XtensaOpcodeOps fpu_ops[] = {
.name = "add.s",
.translate = translate_add_s,
.coprocessor = 0x1,
}, {
.name = "addexp.d",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "addexp.s",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "addexpm.d",
.translate = translate_mov_s,
.coprocessor = 0x1,
}, {
.name = "addexpm.s",
.translate = translate_mov_s,
.coprocessor = 0x1,
}, {
.name = "ceil.d",
.translate = translate_ftoi_d,
@ -7375,6 +7423,22 @@ static const XtensaOpcodeOps fpu_ops[] = {
.name = "cvts.d",
.translate = translate_cvts_d,
.coprocessor = 0x1,
}, {
.name = "div0.d",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "div0.s",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "divn.d",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "divn.s",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "float.d",
.translate = translate_float_d,
@ -7475,6 +7539,30 @@ static const XtensaOpcodeOps fpu_ops[] = {
.name = "madd.s",
.translate = translate_madd_s,
.coprocessor = 0x1,
}, {
.name = "maddn.d",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "maddn.s",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "mkdadj.d",
.translate = translate_mkdadj_d,
.coprocessor = 0x1,
}, {
.name = "mkdadj.s",
.translate = translate_mkdadj_s,
.coprocessor = 0x1,
}, {
.name = "mksadj.d",
.translate = translate_mksadj_d,
.coprocessor = 0x1,
}, {
.name = "mksadj.s",
.translate = translate_mksadj_s,
.coprocessor = 0x1,
}, {
.name = "mov.d",
.translate = translate_mov_d,
@ -7567,6 +7655,14 @@ static const XtensaOpcodeOps fpu_ops[] = {
.name = "neg.s",
.translate = translate_neg_s,
.coprocessor = 0x1,
}, {
.name = "nexp01.d",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "nexp01.s",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "oeq.d",
.translate = translate_compare_d,
@ -7660,6 +7756,14 @@ static const XtensaOpcodeOps fpu_ops[] = {
.par = (const uint32_t[]){true, true, true},
.op_flags = XTENSA_OP_STORE,
.coprocessor = 0x1,
}, {
.name = "sqrt0.d",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "sqrt0.s",
.translate = translate_nop,
.coprocessor = 0x1,
}, {
.name = "ssi",
.translate = translate_ldsti_s,