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target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'
These definitions and declarations are only used by target/arm/, no need to expose them to generic hw/. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-4-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <c48c9829-3dfa-79cf-3042-454fda0d00dc@linaro.org>
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3 changed files with 28 additions and 28 deletions
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@ -35,9 +35,6 @@ typedef struct ARMCPUInfo {
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void (*class_init)(ObjectClass *oc, void *data);
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} ARMCPUInfo;
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void arm_cpu_register(const ARMCPUInfo *info);
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void aarch64_cpu_register(const ARMCPUInfo *info);
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/**
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* ARMCPUClass:
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* @parent_realize: The parent class' realize handler.
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@ -63,29 +60,4 @@ struct AArch64CPUClass {
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ARMCPUClass parent_class;
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};
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void register_cp_regs_for_features(ARMCPU *cpu);
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void init_cpreg_list(ARMCPU *cpu);
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/* Callback functions for the generic timer's timers. */
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void arm_gt_ptimer_cb(void *opaque);
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void arm_gt_vtimer_cb(void *opaque);
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void arm_gt_htimer_cb(void *opaque);
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void arm_gt_stimer_cb(void *opaque);
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void arm_gt_hvtimer_cb(void *opaque);
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#define ARM_AFF0_SHIFT 0
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#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
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#define ARM_AFF1_SHIFT 8
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#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
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#define ARM_AFF2_SHIFT 16
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#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
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#define ARM_AFF3_SHIFT 32
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#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
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#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
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#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
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#define ARM64_AFFINITY_MASK \
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(ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
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#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
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#endif
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@ -1116,11 +1116,33 @@ struct ArchCPU {
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uint64_t gt_cntfrq_hz;
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};
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/* Callback functions for the generic timer's timers. */
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void arm_gt_ptimer_cb(void *opaque);
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void arm_gt_vtimer_cb(void *opaque);
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void arm_gt_htimer_cb(void *opaque);
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void arm_gt_stimer_cb(void *opaque);
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void arm_gt_hvtimer_cb(void *opaque);
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unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
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void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
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void arm_cpu_post_init(Object *obj);
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#define ARM_AFF0_SHIFT 0
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#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
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#define ARM_AFF1_SHIFT 8
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#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
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#define ARM_AFF2_SHIFT 16
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#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
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#define ARM_AFF3_SHIFT 32
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#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
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#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
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#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
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#define ARM64_AFFINITY_MASK \
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(ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
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#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
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uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
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#ifndef CONFIG_USER_ONLY
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@ -183,6 +183,12 @@ static inline int r14_bank_number(int mode)
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return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
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}
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void arm_cpu_register(const ARMCPUInfo *info);
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void aarch64_cpu_register(const ARMCPUInfo *info);
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void register_cp_regs_for_features(ARMCPU *cpu);
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void init_cpreg_list(ARMCPU *cpu);
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void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
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void arm_translate_init(void);
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