mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
ide: pass down DriveInfo instead of BlockDriverState
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
parent
ddd9bbd93b
commit
f455e98cf4
12
hw/ide.h
12
hw/ide.h
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@ -5,23 +5,23 @@
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/* ide-isa.c */
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void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
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BlockDriverState *hd0, BlockDriverState *hd1);
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DriveInfo *hd0, DriveInfo *hd1);
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/* ide-pci.c */
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void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
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void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
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int secondary_ide_enabled);
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void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
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qemu_irq *pic);
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void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
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qemu_irq *pic);
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/* ide-macio.c */
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
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int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
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void *dbdma, int channel, qemu_irq dma_irq);
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/* ide-mmio.c */
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void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
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qemu_irq irq, int shift,
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BlockDriverState *hd0, BlockDriverState *hd1);
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DriveInfo *hd0, DriveInfo *hd1);
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#endif /* HW_IDE_H */
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@ -2506,7 +2506,7 @@ void ide_reset(IDEState *s)
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s->media_changed = 0;
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}
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void ide_init2(IDEBus *bus, BlockDriverState *hd0, BlockDriverState *hd1,
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void ide_init2(IDEBus *bus, DriveInfo *hd0, DriveInfo *hd1,
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qemu_irq irq)
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{
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IDEState *s;
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@ -2518,7 +2518,10 @@ void ide_init2(IDEBus *bus, BlockDriverState *hd0, BlockDriverState *hd1,
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s = bus->ifs + i;
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s->bus = bus;
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s->unit = i;
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s->bs = (i == 0) ? hd0 : hd1;
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if (i == 0 && hd0)
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s->bs = hd0->bdrv;
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if (i == 1 && hd1)
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s->bs = hd1->bdrv;
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s->io_buffer = qemu_blockalign(s->bs, IDE_DMA_BUF_SECTORS*512 + 4);
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if (s->bs) {
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bdrv_get_geometry(s->bs, &nb_sectors);
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@ -528,7 +528,7 @@ uint32_t ide_data_readw(void *opaque, uint32_t addr);
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void ide_data_writel(void *opaque, uint32_t addr, uint32_t val);
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uint32_t ide_data_readl(void *opaque, uint32_t addr);
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void ide_init2(IDEBus *bus, BlockDriverState *hd0, BlockDriverState *hd1,
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void ide_init2(IDEBus *bus, DriveInfo *hd0, DriveInfo *hd1,
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qemu_irq irq);
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void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
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@ -58,7 +58,7 @@ static int isa_ide_load(QEMUFile* f, void *opaque, int version_id)
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}
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void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
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BlockDriverState *hd0, BlockDriverState *hd1)
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DriveInfo *hd0, DriveInfo *hd1)
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{
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ISAIDEState *s;
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@ -334,7 +334,7 @@ static void pmac_ide_reset(void *opaque)
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/* hd_table must contain 4 block drivers */
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/* PowerMac uses memory mapped registers, not I/O. Return the memory
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I/O index to access the ide. */
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
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int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
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void *dbdma, int channel, qemu_irq dma_irq)
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{
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MACIOIDEState *d;
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@ -555,7 +555,7 @@ static int dscm1xxxx_detach(void *opaque)
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return 0;
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}
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PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv)
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PCMCIACardState *dscm1xxxx_init(DriveInfo *bdrv)
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{
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MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState));
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md->card.state = md;
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@ -124,7 +124,7 @@ static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id)
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void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
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qemu_irq irq, int shift,
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BlockDriverState *hd0, BlockDriverState *hd1)
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DriveInfo *hd0, DriveInfo *hd1)
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{
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MMIOState *s = qemu_mallocz(sizeof(MMIOState));
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IDEBus *bus = qemu_mallocz(sizeof(*bus));
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11
hw/ide/pci.c
11
hw/ide/pci.c
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@ -375,7 +375,7 @@ static void cmd646_reset(void *opaque)
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}
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/* CMD646 PCI IDE controller */
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void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
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void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
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int secondary_ide_enabled)
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{
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PCIIDEState *d;
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@ -443,12 +443,11 @@ static void piix3_reset(void *opaque)
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
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void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
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qemu_irq *pic)
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{
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PCIIDEState *d;
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uint8_t *pci_conf;
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int i;
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/* register a function 1 of PIIX3 */
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d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
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@ -475,16 +474,12 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
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ide_init_ioport(&d->bus[1], 0x170, 0x376);
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for (i = 0; i < 4; i++)
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if (hd_table[i])
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hd_table[i]->private = &d->dev;
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register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
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}
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
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void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
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qemu_irq *pic)
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{
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PCIIDEState *d;
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@ -775,7 +775,7 @@ void mips_malta_init (ram_addr_t ram_size,
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i2c_bus *smbus;
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int i;
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DriveInfo *dinfo;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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BlockDriverState *fd[MAX_FD];
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int fl_idx = 0;
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int fl_sectors = 0;
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}
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for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
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dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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hd[i] = dinfo ? dinfo->bdrv : NULL;
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hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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}
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piix4_devfn = piix4_init(pci_bus, 80);
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@ -156,7 +156,7 @@ void mips_r4k_init (ram_addr_t ram_size,
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RTCState *rtc_state;
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int i;
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qemu_irq *i8259;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *dinfo;
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/* init CPUs */
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}
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for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
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dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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hd[i] = dinfo ? dinfo->bdrv : NULL;
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hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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}
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for(i = 0; i < MAX_IDE_BUS; i++)
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15
hw/pc.c
15
hw/pc.c
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@ -264,7 +264,7 @@ static int pc_boot_set(void *opaque, const char *boot_device)
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/* hd_table must contain 4 block drivers */
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
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const char *boot_device, BlockDriverState **hd_table)
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const char *boot_device, DriveInfo **hd_table)
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{
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RTCState *s = rtc_state;
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int nbds, bds[3] = { 0, };
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rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
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if (hd_table[0])
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cmos_init_hd(0x19, 0x1b, hd_table[0]);
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cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
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if (hd_table[1])
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cmos_init_hd(0x1a, 0x24, hd_table[1]);
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cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
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val = 0;
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for (i = 0; i < 4; i++) {
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geometry. It is always such that: 1 <= sects <= 63, 1
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<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
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geometry can be different if a translation is done. */
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translation = bdrv_get_translation_hint(hd_table[i]);
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translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
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if (translation == BIOS_ATA_TRANSLATION_AUTO) {
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bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors);
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bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors);
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if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
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/* No translation. */
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translation = 0;
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qemu_irq *i8259;
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IsaIrqState *isa_irq_state;
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DriveInfo *dinfo;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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BlockDriverState *fd[MAX_FD];
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int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
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void *fw_cfg;
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}
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for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
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dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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hd[i] = dinfo ? dinfo->bdrv : NULL;
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hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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}
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if (pci_enabled) {
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@ -1,6 +1,7 @@
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/* PCMCIA/Cardbus */
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#include "qemu-common.h"
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#include "sysemu.h"
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typedef struct {
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qemu_irq irq;
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#define CISTPL_ENDMARK 0xff
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/* dscm1xxxx.c */
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PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv);
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PCMCIACardState *dscm1xxxx_init(DriveInfo *bdrv);
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@ -107,8 +107,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
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qemu_irq *dummy_irq;
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int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index;
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int ppc_boot_device;
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DriveInfo *dinfo;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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void *fw_cfg;
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void *dbdma;
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uint8_t *vga_bios_ptr;
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@ -316,8 +315,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
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exit(1);
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}
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for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
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dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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hd[i] = dinfo ? dinfo->bdrv : NULL;
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hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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}
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dbdma = DBDMA_init(&dbdma_mem_index);
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pci_cmd646_ide_init(pci_bus, hd, 0);
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@ -137,8 +137,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
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int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
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int escc_mem_index, ide_mem_index[2];
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uint16_t ppc_boot_device;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *dinfo;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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void *fw_cfg;
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void *dbdma;
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uint8_t *vga_bios_ptr;
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@ -331,19 +330,15 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
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}
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/* First IDE channel is a MAC IDE on the MacIO bus */
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dinfo = drive_get(IF_IDE, 0, 0);
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hd[0] = dinfo ? dinfo->bdrv : NULL;
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dinfo = drive_get(IF_IDE, 0, 1);
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hd[1] = dinfo ? dinfo->bdrv : NULL;
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hd[0] = drive_get(IF_IDE, 0, 0);
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hd[1] = drive_get(IF_IDE, 0, 1);
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dbdma = DBDMA_init(&dbdma_mem_index);
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ide_mem_index[0] = -1;
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ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
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/* Second IDE channel is a CMD646 on the PCI bus */
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dinfo = drive_get(IF_IDE, 1, 0);
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hd[0] = dinfo ? dinfo->bdrv : NULL;
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dinfo = drive_get(IF_IDE, 1, 1);
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hd[1] = dinfo ? dinfo->bdrv : NULL;
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hd[0] = drive_get(IF_IDE, 1, 0);
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hd[1] = drive_get(IF_IDE, 1, 1);
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hd[3] = hd[2] = NULL;
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pci_cmd646_ide_init(pci_bus, hd, 0);
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@ -563,7 +563,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
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qemu_irq *i8259;
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int ppc_boot_device;
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DriveInfo *dinfo;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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BlockDriverState *fd[MAX_FD];
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sysctrl = qemu_mallocz(sizeof(sysctrl_t));
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@ -703,8 +703,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
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}
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for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
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dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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hd[i] = dinfo ? dinfo->bdrv : NULL;
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hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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}
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for(i = 0; i < MAX_IDE_BUS; i++) {
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2
hw/r2d.c
2
hw/r2d.c
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@ -231,7 +231,7 @@ static void r2d_init(ram_addr_t ram_size,
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/* onboard CF (True IDE mode, Master only). */
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if ((dinfo = drive_get(IF_IDE, 0, 0)) != NULL)
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mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
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dinfo->bdrv, NULL);
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dinfo, NULL);
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/* NIC: rtl8139 on-board, and 2 slots. */
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for (i = 0; i < nb_nics; i++)
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@ -754,7 +754,7 @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
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return;
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bs = dinfo->bdrv;
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if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
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md = dscm1xxxx_init(bs);
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md = dscm1xxxx_init(dinfo);
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pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
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}
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}
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@ -566,7 +566,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
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long initrd_size, kernel_size;
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PCIBus *pci_bus, *pci_bus2, *pci_bus3;
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qemu_irq *irq;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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BlockDriverState *fd[MAX_FD];
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void *fw_cfg;
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DriveInfo *dinfo;
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@ -617,9 +617,8 @@ static void sun4uv_init(ram_addr_t RAM_size,
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exit(1);
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}
|
||||
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
|
||||
dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS,
|
||||
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
|
||||
i % MAX_IDE_DEVS);
|
||||
hd[i] = dinfo ? dinfo->bdrv : NULL;
|
||||
}
|
||||
|
||||
pci_cmd646_ide_init(pci_bus, hd, 1);
|
||||
|
|
Loading…
Reference in a new issue