mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
CRIS support in toplevel, by Edgar E. Iglesias.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3363 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
94cff60a02
commit
f1ccf90477
7 changed files with 143 additions and 2 deletions
62
cpu-exec.c
62
cpu-exec.c
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@ -210,6 +210,10 @@ static inline TranslationBlock *tb_find_fast(void)
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flags = env->ps;
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cs_base = 0;
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pc = env->pc;
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#elif defined(TARGET_CRIS)
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flags = 0;
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cs_base = 0;
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pc = env->pc;
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#else
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#error unsupported CPU
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#endif
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@ -284,6 +288,7 @@ int cpu_exec(CPUState *env1)
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#elif defined(TARGET_PPC)
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#elif defined(TARGET_MIPS)
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#elif defined(TARGET_SH4)
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#elif defined(TARGET_CRIS)
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/* XXXXX */
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#else
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#error unsupported target CPU
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@ -335,6 +340,8 @@ int cpu_exec(CPUState *env1)
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do_interrupt(env);
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#elif defined(TARGET_ALPHA)
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do_interrupt(env);
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#elif defined(TARGET_CRIS)
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do_interrupt(env);
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#elif defined(TARGET_M68K)
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do_interrupt(0);
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#endif
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@ -385,7 +392,7 @@ int cpu_exec(CPUState *env1)
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cpu_loop_exit();
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}
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#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
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defined(TARGET_PPC) || defined(TARGET_ALPHA)
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defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
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if (interrupt_request & CPU_INTERRUPT_HALT) {
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env->interrupt_request &= ~CPU_INTERRUPT_HALT;
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env->halted = 1;
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@ -517,6 +524,11 @@ int cpu_exec(CPUState *env1)
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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do_interrupt(env);
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}
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#elif defined(TARGET_CRIS)
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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do_interrupt(env);
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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}
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#elif defined(TARGET_M68K)
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if (interrupt_request & CPU_INTERRUPT_HARD
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&& ((env->sr & SR_I) >> SR_I_SHIFT)
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@ -576,6 +588,8 @@ int cpu_exec(CPUState *env1)
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cpu_dump_state(env, logfile, fprintf, 0);
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#elif defined(TARGET_ALPHA)
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cpu_dump_state(env, logfile, fprintf, 0);
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#elif defined(TARGET_CRIS)
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cpu_dump_state(env, logfile, fprintf, 0);
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#else
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#error unsupported target CPU
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#endif
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@ -769,6 +783,7 @@ int cpu_exec(CPUState *env1)
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#elif defined(TARGET_MIPS)
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#elif defined(TARGET_SH4)
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#elif defined(TARGET_ALPHA)
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#elif defined(TARGET_CRIS)
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/* XXXXX */
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#else
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#error unsupported target CPU
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@ -1200,6 +1215,51 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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/* never comes here */
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return 1;
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}
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#elif defined (TARGET_CRIS)
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static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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int is_write, sigset_t *old_set,
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void *puc)
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{
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TranslationBlock *tb;
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int ret;
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if (cpu_single_env)
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env = cpu_single_env; /* XXX: find a correct solution for multithread */
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set);
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#endif
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/* XXX: locking issue */
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if (is_write && page_unprotect(h2g(address), pc, puc)) {
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return 1;
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}
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/* see if it is an MMU fault */
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ret = cpu_cris_handle_mmu_fault(env, address, is_write, 1, 0);
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if (ret < 0)
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return 0; /* not an MMU fault */
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if (ret == 0)
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return 1; /* the MMU fault was handled without causing real CPU fault */
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/* now we have a real cpu fault */
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, puc);
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}
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#if 0
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printf("PF exception: NIP=0x%08x error=0x%x %p\n",
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env->nip, env->error_code, tb);
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#endif
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/* we restore the process signal mask as the sigreturn should
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do it (XXX: use sigsetjmp) */
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sigprocmask(SIG_SETMASK, old_set, NULL);
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cpu_loop_exit();
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/* never comes here */
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return 1;
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}
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#else
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#error unsupported target CPU
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#endif
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@ -617,6 +617,8 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
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is_user = ((env->ps >> 3) & 3);
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#elif defined (TARGET_M68K)
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is_user = ((env->sr & SR_S) == 0);
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#elif defined (TARGET_CRIS)
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is_user = (0);
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#else
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#error unimplemented CPU
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#endif
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4
exec.c
4
exec.c
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@ -2066,6 +2066,8 @@ static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
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#endif
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#ifdef TARGET_SPARC
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do_unassigned_access(addr, 0, 0, 0);
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#elif TARGET_CRIS
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do_unassigned_access(addr, 0, 0, 0);
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#endif
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return 0;
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}
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@ -2077,6 +2079,8 @@ static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_
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#endif
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#ifdef TARGET_SPARC
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do_unassigned_access(addr, 1, 0, 0);
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#elif TARGET_CRIS
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do_unassigned_access(addr, 1, 0, 0);
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#endif
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}
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66
gdbstub.c
66
gdbstub.c
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@ -728,6 +728,66 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
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for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
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for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
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}
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#elif defined (TARGET_CRIS)
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static int cris_save_32 (unsigned char *d, uint32_t value)
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{
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*d++ = (value);
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*d++ = (value >>= 8);
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*d++ = (value >>= 8);
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*d++ = (value >>= 8);
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return 4;
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}
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static int cris_save_16 (unsigned char *d, uint32_t value)
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{
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*d++ = (value);
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*d++ = (value >>= 8);
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return 2;
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}
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static int cris_save_8 (unsigned char *d, uint32_t value)
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{
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*d++ = (value);
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return 1;
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}
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/* FIXME: this will bug on archs not supporting unaligned word accesses. */
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static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
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{
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uint8_t *ptr = mem_buf;
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uint8_t srs;
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int i;
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for (i = 0; i < 16; i++)
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ptr += cris_save_32 (ptr, env->regs[i]);
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srs = env->pregs[SR_SRS];
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ptr += cris_save_8 (ptr, env->pregs[0]);
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ptr += cris_save_8 (ptr, env->pregs[1]);
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ptr += cris_save_32 (ptr, env->pregs[2]);
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ptr += cris_save_8 (ptr, srs);
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ptr += cris_save_16 (ptr, env->pregs[4]);
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for (i = 5; i < 16; i++)
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ptr += cris_save_32 (ptr, env->pregs[i]);
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ptr += cris_save_32 (ptr, env->pc);
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for (i = 0; i < 16; i++)
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ptr += cris_save_32 (ptr, env->sregs[srs][i]);
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return ((uint8_t *)ptr - mem_buf);
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}
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static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
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{
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uint32_t *ptr = (uint32_t *)mem_buf;
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int i;
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#define LOAD(x) (x)=*ptr++;
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for (i = 0; i < 16; i++) LOAD(env->regs[i]);
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LOAD (env->pc);
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}
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#else
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static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
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{
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@ -745,7 +805,7 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
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const char *p;
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int ch, reg_size, type;
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char buf[4096];
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uint8_t mem_buf[2000];
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uint8_t mem_buf[4096];
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uint32_t *registers;
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target_ulong addr, len;
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@ -776,6 +836,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
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env->pc = addr;
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#elif defined (TARGET_MIPS)
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env->PC[env->current_tc] = addr;
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#elif defined (TARGET_CRIS)
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env->pc = addr;
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#endif
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}
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#ifdef CONFIG_USER_ONLY
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@ -800,6 +862,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
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env->pc = addr;
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#elif defined (TARGET_MIPS)
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env->PC[env->current_tc] = addr;
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#elif defined (TARGET_CRIS)
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env->pc = addr;
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#endif
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}
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cpu_single_step(env, 1);
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@ -67,6 +67,9 @@
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#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
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#elif defined (TARGET_M68K)
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#define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
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#elif defined (TARGET_CRIS)
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/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */
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#define CPU_MEM_INDEX (0)
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#else
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#error unsupported CPU
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#endif
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@ -90,6 +93,9 @@
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#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
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#elif defined (TARGET_M68K)
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#define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
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#elif defined (TARGET_CRIS)
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/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */
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#define CPU_MEM_INDEX (0)
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#else
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#error unsupported CPU
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#endif
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2
vl.c
2
vl.c
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@ -7390,6 +7390,8 @@ void register_machines(void)
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#elif defined(TARGET_M68K)
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qemu_register_machine(&mcf5208evb_machine);
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qemu_register_machine(&an5206_machine);
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#elif defined(TARGET_CRIS)
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qemu_register_machine(&bareetraxfs_machine);
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#else
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#error unsupported CPU
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#endif
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3
vl.h
3
vl.h
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@ -1173,6 +1173,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
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void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
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void acpi_bios_init(void);
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/* Axis ETRAX. */
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extern QEMUMachine bareetraxfs_machine;
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/* pc.c */
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extern QEMUMachine pc_machine;
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extern QEMUMachine isapc_machine;
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