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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
tcg-ppc: Use TCGMemOp within qemu_ldst routines
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
091d567771
commit
f1a16dcdd5
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@ -525,7 +525,7 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg,
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static void add_qemu_ldst_label (TCGContext *s,
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int is_ld,
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int opc,
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TCGMemOp opc,
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int data_reg,
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int data_reg2,
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int addrlo_reg,
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@ -575,7 +575,7 @@ static void *st_trampolines[4];
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Clobbers R1 and R2. */
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static void tcg_out_tlb_check(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2,
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TCGReg addrlo, TCGReg addrhi, int s_bits,
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TCGReg addrlo, TCGReg addrhi, TCGMemOp s_bits,
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int mem_index, int is_load, uint8_t **label_ptr)
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{
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int cmp_off =
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@ -647,10 +647,11 @@ static void tcg_out_tlb_check(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2,
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}
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#endif
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static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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TCGReg addrlo, datalo, datahi, rbase;
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int bswap;
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TCGMemOp bswap = opc & MO_BSWAP;
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TCGMemOp s_bits = opc & MO_SIZE;
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#ifdef CONFIG_SOFTMMU
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int mem_index;
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TCGReg addrhi;
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@ -658,7 +659,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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#endif
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datalo = *args++;
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datahi = (opc == 3 ? *args++ : 0);
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datahi = (s_bits == MO_64 ? *args++ : 0);
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addrlo = *args++;
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#ifdef CONFIG_SOFTMMU
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@ -666,31 +667,25 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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mem_index = *args;
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tcg_out_tlb_check(s, TCG_REG_R3, TCG_REG_R4, TCG_REG_R0, addrlo,
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addrhi, opc & 3, mem_index, 0, &label_ptr);
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addrhi, s_bits, mem_index, 0, &label_ptr);
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rbase = TCG_REG_R3;
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#else /* !CONFIG_SOFTMMU */
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 0;
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#else
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bswap = 1;
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#endif
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switch (opc) {
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switch (opc & MO_SSIZE) {
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default:
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case 0:
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case MO_UB:
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tcg_out32(s, LBZX | TAB(datalo, rbase, addrlo));
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break;
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case 0|4:
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case MO_SB:
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tcg_out32(s, LBZX | TAB(datalo, rbase, addrlo));
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tcg_out32(s, EXTSB | RA(datalo) | RS(datalo));
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break;
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case 1:
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case MO_UW:
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tcg_out32(s, (bswap ? LHBRX : LHZX) | TAB(datalo, rbase, addrlo));
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break;
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case 1|4:
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case MO_SW:
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if (bswap) {
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tcg_out32(s, LHBRX | TAB(datalo, rbase, addrlo));
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tcg_out32(s, EXTSH | RA(datalo) | RS(datalo));
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@ -698,10 +693,10 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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tcg_out32(s, LHAX | TAB(datalo, rbase, addrlo));
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}
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break;
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case 2:
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case MO_UL:
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tcg_out32(s, (bswap ? LWBRX : LWZX) | TAB(datalo, rbase, addrlo));
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break;
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case 3:
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case MO_Q:
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if (bswap) {
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tcg_out32(s, ADDI | RT(TCG_REG_R0) | RA(addrlo) | 4);
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tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
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@ -725,10 +720,11 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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#endif
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}
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static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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TCGReg addrlo, datalo, datahi, rbase;
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int bswap;
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TCGMemOp bswap = opc & MO_BSWAP;
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TCGMemOp s_bits = opc & MO_SIZE;
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#ifdef CONFIG_SOFTMMU
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int mem_index;
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TCGReg addrhi;
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@ -736,7 +732,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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#endif
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datalo = *args++;
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datahi = (opc == 3 ? *args++ : 0);
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datahi = (s_bits == MO_64 ? *args++ : 0);
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addrlo = *args++;
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#ifdef CONFIG_SOFTMMU
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@ -744,28 +740,24 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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mem_index = *args;
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tcg_out_tlb_check(s, TCG_REG_R3, TCG_REG_R4, TCG_REG_R0, addrlo,
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addrhi, opc & 3, mem_index, 0, &label_ptr);
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addrhi, s_bits, mem_index, 0, &label_ptr);
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rbase = TCG_REG_R3;
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#else /* !CONFIG_SOFTMMU */
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 0;
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#else
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bswap = 1;
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#endif
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switch (opc) {
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case 0:
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switch (s_bits) {
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case MO_8:
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tcg_out32(s, STBX | SAB(datalo, rbase, addrlo));
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break;
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case 1:
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case MO_16:
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tcg_out32(s, (bswap ? STHBRX : STHX) | SAB(datalo, rbase, addrlo));
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break;
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case 2:
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case MO_32:
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default:
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tcg_out32(s, (bswap ? STWBRX : STWX) | SAB(datalo, rbase, addrlo));
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break;
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case 3:
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case MO_64:
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if (bswap) {
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tcg_out32(s, ADDI | RT(TCG_REG_R0) | RA(addrlo) | 4);
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tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
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@ -791,6 +783,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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TCGReg ir, datalo, datahi;
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TCGMemOp opc = l->opc & MO_SSIZE;
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reloc_pc14 (l->label_ptr[0], (uintptr_t)s->code_ptr);
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@ -806,22 +799,20 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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}
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tcg_out_movi(s, TCG_TYPE_I32, ir++, l->mem_index);
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tcg_out32(s, MFSPR | RT(ir++) | LR);
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tcg_out_b(s, LK, (uintptr_t)ld_trampolines[l->opc & 3]);
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tcg_out_b(s, LK, (uintptr_t)ld_trampolines[opc & MO_SIZE]);
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datalo = l->datalo_reg;
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switch (l->opc) {
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case 0|4:
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switch (opc) {
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case MO_SB:
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tcg_out32(s, EXTSB | RA(datalo) | RS(TCG_REG_R3));
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break;
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case 1|4:
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case MO_SW:
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tcg_out32(s, EXTSH | RA(datalo) | RS(TCG_REG_R3));
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break;
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case 0:
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case 1:
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case 2:
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default:
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tcg_out_mov(s, TCG_TYPE_I32, datalo, TCG_REG_R3);
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break;
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case 3:
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case MO_Q:
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datahi = l->datahi_reg;
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if (datalo != TCG_REG_R3) {
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tcg_out_mov(s, TCG_TYPE_I32, datalo, TCG_REG_R4);
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@ -842,6 +833,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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TCGReg ir, datalo;
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TCGMemOp s_bits = l->opc & MO_SIZE;
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reloc_pc14 (l->label_ptr[0], (tcg_target_long) s->code_ptr);
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@ -857,19 +849,19 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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}
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datalo = l->datalo_reg;
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switch (l->opc) {
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case 0:
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switch (s_bits) {
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case MO_8:
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tcg_out32(s, (RLWINM | RA (ir) | RS (datalo)
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| SH (0) | MB (24) | ME (31)));
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break;
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case 1:
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case MO_16:
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tcg_out32(s, (RLWINM | RA (ir) | RS (datalo)
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| SH (0) | MB (16) | ME (31)));
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break;
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case 2:
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default:
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tcg_out_mov(s, TCG_TYPE_I32, ir, datalo);
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break;
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case 3:
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case MO_64:
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#ifdef TCG_TARGET_CALL_ALIGN_ARGS
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ir |= 1;
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#endif
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@ -1707,34 +1699,34 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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break;
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case INDEX_op_qemu_ld8u:
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tcg_out_qemu_ld(s, args, 0);
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tcg_out_qemu_ld(s, args, MO_UB);
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break;
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case INDEX_op_qemu_ld8s:
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tcg_out_qemu_ld(s, args, 0 | 4);
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tcg_out_qemu_ld(s, args, MO_SB);
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break;
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case INDEX_op_qemu_ld16u:
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tcg_out_qemu_ld(s, args, 1);
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tcg_out_qemu_ld(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_ld16s:
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tcg_out_qemu_ld(s, args, 1 | 4);
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tcg_out_qemu_ld(s, args, MO_TESW);
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break;
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case INDEX_op_qemu_ld32:
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tcg_out_qemu_ld(s, args, 2);
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tcg_out_qemu_ld(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_ld64:
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tcg_out_qemu_ld(s, args, 3);
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tcg_out_qemu_ld(s, args, MO_TEQ);
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break;
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case INDEX_op_qemu_st8:
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tcg_out_qemu_st(s, args, 0);
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tcg_out_qemu_st(s, args, MO_UB);
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break;
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case INDEX_op_qemu_st16:
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tcg_out_qemu_st(s, args, 1);
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tcg_out_qemu_st(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_st32:
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tcg_out_qemu_st(s, args, 2);
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tcg_out_qemu_st(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_st64:
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tcg_out_qemu_st(s, args, 3);
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tcg_out_qemu_st(s, args, MO_TEQ);
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break;
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case INDEX_op_ext8s_i32:
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