mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
Second half of mipssim support, plus documentation improvements.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3401 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
6bf5b4e8a8
commit
f0fc6f8fbc
3 changed files with 440 additions and 2 deletions
167
hw/mips_mipssim.c
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167
hw/mips_mipssim.c
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@ -0,0 +1,167 @@
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/*
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* QEMU/mipssim emulation
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*
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* Emulates a very simple machine model similiar to the one use by the
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* proprietary MIPS emulator.
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*/
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#include "vl.h"
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin"
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#else
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#define BIOS_FILENAME "mipsel_bios.bin"
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#endif
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#ifdef TARGET_MIPS64
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
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#else
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
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#endif
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#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
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static void load_kernel (CPUState *env)
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{
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int64_t entry, kernel_low, kernel_high;
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long kernel_size;
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long initrd_size;
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ram_addr_t initrd_offset;
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kernel_size = load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND,
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&entry, &kernel_low, &kernel_high);
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if (kernel_size >= 0) {
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if ((entry & ~0x7fffffffULL) == 0x80000000)
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entry = (int32_t)entry;
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env->PC[env->current_tc] = entry;
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} else {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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env->kernel_filename);
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exit(1);
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}
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/* load initrd */
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initrd_size = 0;
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initrd_offset = 0;
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if (env->initrd_filename) {
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initrd_size = get_image_size (env->initrd_filename);
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if (initrd_size > 0) {
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initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
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if (initrd_offset + initrd_size > env->ram_size) {
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fprintf(stderr,
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"qemu: memory too small for initial ram disk '%s'\n",
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env->initrd_filename);
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exit(1);
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}
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initrd_size = load_image(env->initrd_filename,
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phys_ram_base + initrd_offset);
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}
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if (initrd_size == (target_ulong) -1) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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env->initrd_filename);
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exit(1);
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}
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}
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}
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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cpu_mips_register(env, NULL);
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if (env->kernel_filename)
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load_kernel (env);
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}
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static void
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mips_mipssim_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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char buf[1024];
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unsigned long bios_offset;
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CPUState *env;
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int ret;
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mips_def_t *def;
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/* Init CPUs. */
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if (cpu_model == NULL) {
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#ifdef TARGET_MIPS64
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cpu_model = "5Kf";
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#else
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cpu_model = "24Kf";
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#endif
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}
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if (mips_find_by_name(cpu_model, &def) != 0)
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def = NULL;
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env = cpu_init();
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cpu_mips_register(env, def);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* Allocate RAM. */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* Map the BIOS / boot exception handler. */
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bios_offset = ram_size + vga_ram_size;
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/* Load a BIOS / boot exception handler image. */
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_image(buf, phys_ram_base + bios_offset);
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if ((ret < 0 || ret > BIOS_SIZE) && !kernel_filename) {
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/* Bail out if we have neither a kernel image nor boot vector code. */
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fprintf(stderr,
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"qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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buf);
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exit(1);
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} else {
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/* We have a boot vector start address. */
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env->PC[env->current_tc] = (target_long)0xbfc00000;
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cpu_register_physical_memory(0x1fc00000LL,
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ret, bios_offset | IO_MEM_ROM);
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}
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if (kernel_filename) {
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env->ram_size = ram_size;
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env->kernel_filename = kernel_filename;
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env->kernel_cmdline = kernel_cmdline;
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env->initrd_filename = initrd_filename;
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load_kernel(env);
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}
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/* Init CPU internal devices. */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irqctrl_init();
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/* Register 64 KB of ISA IO space at 0x1fd00000. */
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isa_mmio_init(0x1fd00000, 0x00010000);
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/* A single 16450 sits at offset 0x3f8. It is attached to
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MIPS CPU INT2, which is interrupt 4. */
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if (serial_hds[0])
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serial_init(0x3f8, env->irq[4], serial_hds[0]);
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "mipsnet") == 0) {
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/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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mipsnet_init(0x4200, env->irq[2], &nd_table[0]);
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} else if (strcmp(nd_table[0].model, "?") == 0) {
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fprintf(stderr, "qemu: Supported NICs: mipsnet\n");
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exit (1);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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}
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}
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QEMUMachine mips_mipssim_machine = {
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"mipssim",
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"MIPS MIPSsim platform",
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mips_mipssim_init,
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};
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269
hw/mipsnet.c
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269
hw/mipsnet.c
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@ -0,0 +1,269 @@
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#include "vl.h"
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#define DEBUG_MIPSNET_SEND
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#define DEBUG_MIPSNET_RECEIVE
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//#define DEBUG_MIPSNET_DATA
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#define DEBUG_MIPSNET_IRQ
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/* MIPSnet register offsets */
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#define MIPSNET_DEV_ID 0x00
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# define MIPSNET_DEV_ID_STRING "MIPSNET0"
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#define MIPSNET_BUSY 0x08
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#define MIPSNET_RX_DATA_COUNT 0x0c
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#define MIPSNET_TX_DATA_COUNT 0x10
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#define MIPSNET_INT_CTL 0x14
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# define MIPSNET_INTCTL_TXDONE 0x00000001
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# define MIPSNET_INTCTL_RXDONE 0x00000002
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# define MIPSNET_INTCTL_TESTBIT 0x80000000
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#define MIPSNET_INTERRUPT_INFO 0x18
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#define MIPSNET_RX_DATA_BUFFER 0x1c
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#define MIPSNET_TX_DATA_BUFFER 0x20
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#define MAX_ETH_FRAME_SIZE 1514
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typedef struct MIPSnetState {
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uint32_t busy;
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uint32_t rx_count;
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uint32_t rx_read;
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uint32_t tx_count;
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uint32_t tx_written;
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uint32_t intctl;
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uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
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uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
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qemu_irq irq;
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VLANClientState *vc;
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NICInfo *nd;
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} MIPSnetState;
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static void mipsnet_reset(MIPSnetState *s)
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{
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s->busy = 1;
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s->rx_count = 0;
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s->rx_read = 0;
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s->tx_count = 0;
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s->tx_written = 0;
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s->intctl = 0;
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memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
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memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
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}
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static void mipsnet_update_irq(MIPSnetState *s)
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{
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int isr = !!s->intctl;
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#ifdef DEBUG_MIPSNET_IRQ
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printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
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#endif
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qemu_set_irq(s->irq, isr);
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}
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static int mipsnet_buffer_full(MIPSnetState *s)
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{
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if (s->rx_count >= MAX_ETH_FRAME_SIZE)
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return 1;
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return 0;
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}
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static int mipsnet_can_receive(void *opaque)
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{
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MIPSnetState *s = opaque;
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if (s->busy)
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return 0;
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return !mipsnet_buffer_full(s);
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}
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static void mipsnet_receive(void *opaque, const uint8_t *buf, int size)
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{
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MIPSnetState *s = opaque;
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#ifdef DEBUG_MIPSNET_RECEIVE
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printf("mipsnet: receiving len=%d\n", size);
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#endif
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if (!mipsnet_can_receive(opaque))
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return;
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s->busy = 1;
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/* Just accept everything. */
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/* Write packet data. */
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memcpy(s->rx_buffer, buf, size);
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s->rx_count = size;
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s->rx_read = 0;
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/* Now we can signal we have received something. */
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s->intctl |= MIPSNET_INTCTL_RXDONE;
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mipsnet_update_irq(s);
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}
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static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
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{
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MIPSnetState *s = opaque;
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int ret = 0;
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const char *devid = MIPSNET_DEV_ID_STRING;
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addr &= 0x3f;
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switch (addr) {
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case MIPSNET_DEV_ID:
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ret = *((uint32_t *)&devid);
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break;
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case MIPSNET_DEV_ID + 4:
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ret = *((uint32_t *)(&devid + 4));
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break;
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case MIPSNET_BUSY:
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ret = s->busy;
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break;
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case MIPSNET_RX_DATA_COUNT:
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ret = s->rx_count;
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break;
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case MIPSNET_TX_DATA_COUNT:
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ret = s->tx_count;
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break;
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case MIPSNET_INT_CTL:
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ret = s->intctl;
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s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
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break;
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case MIPSNET_INTERRUPT_INFO:
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/* XXX: This seems to be a per-VPE interrupt number. */
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ret = 0;
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break;
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case MIPSNET_RX_DATA_BUFFER:
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if (s->rx_count) {
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s->rx_count--;
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ret = s->rx_buffer[s->rx_read++];
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}
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break;
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/* Reads as zero. */
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case MIPSNET_TX_DATA_BUFFER:
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default:
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break;
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}
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#ifdef DEBUG_MIPSNET_DATA
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printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
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#endif
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return ret;
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}
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static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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MIPSnetState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG_MIPSNET_DATA
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printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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switch (addr) {
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case MIPSNET_TX_DATA_COUNT:
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s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
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s->tx_written = 0;
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break;
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case MIPSNET_INT_CTL:
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if (val & MIPSNET_INTCTL_TXDONE) {
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s->intctl &= ~MIPSNET_INTCTL_TXDONE;
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} else if (val & MIPSNET_INTCTL_RXDONE) {
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s->intctl &= ~MIPSNET_INTCTL_RXDONE;
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} else if (val & MIPSNET_INTCTL_TESTBIT) {
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mipsnet_reset(s);
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s->intctl |= MIPSNET_INTCTL_TESTBIT;
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} else if (!val) {
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/* ACK testbit interrupt, flag was cleared on read. */
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}
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s->busy = !!s->intctl;
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mipsnet_update_irq(s);
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break;
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case MIPSNET_TX_DATA_BUFFER:
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s->tx_buffer[s->tx_written++] = val;
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if (s->tx_written == s->tx_count) {
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/* Send buffer. */
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#ifdef DEBUG_MIPSNET_SEND
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printf("mipsnet: sending len=%d\n", s->tx_count);
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#endif
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qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
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s->tx_count = s->tx_written = 0;
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s->intctl |= MIPSNET_INTCTL_TXDONE;
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s->busy = 1;
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mipsnet_update_irq(s);
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}
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break;
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/* Read-only registers */
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case MIPSNET_DEV_ID:
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case MIPSNET_BUSY:
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case MIPSNET_RX_DATA_COUNT:
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case MIPSNET_INTERRUPT_INFO:
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case MIPSNET_RX_DATA_BUFFER:
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default:
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break;
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}
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}
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static void mipsnet_save(QEMUFile *f, void *opaque)
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{
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MIPSnetState *s = opaque;
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qemu_put_be32s(f, &s->busy);
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qemu_put_be32s(f, &s->rx_count);
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qemu_put_be32s(f, &s->rx_read);
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qemu_put_be32s(f, &s->tx_count);
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qemu_put_be32s(f, &s->tx_written);
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qemu_put_be32s(f, &s->intctl);
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qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
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qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
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}
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static int mipsnet_load(QEMUFile *f, void *opaque, int version_id)
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{
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MIPSnetState *s = opaque;
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if (version_id > 0)
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return -EINVAL;
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qemu_get_be32s(f, &s->busy);
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qemu_get_be32s(f, &s->rx_count);
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qemu_get_be32s(f, &s->rx_read);
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qemu_get_be32s(f, &s->tx_count);
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qemu_get_be32s(f, &s->tx_written);
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qemu_get_be32s(f, &s->intctl);
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qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
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qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
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return 0;
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}
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void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
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{
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MIPSnetState *s;
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s = qemu_mallocz(sizeof(MIPSnetState));
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if (!s)
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return;
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register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
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register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
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register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
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register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
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register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
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register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
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s->irq = irq;
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s->nd = nd;
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if (nd && nd->vlan) {
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s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive,
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mipsnet_can_receive, s);
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} else {
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s->vc = NULL;
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}
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snprintf(s->vc->info_str, sizeof(s->vc->info_str),
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"mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
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s->nd->macaddr[0],
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s->nd->macaddr[1],
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s->nd->macaddr[2],
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s->nd->macaddr[3],
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s->nd->macaddr[4],
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s->nd->macaddr[5]);
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mipsnet_reset(s);
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register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
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}
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@ -2037,7 +2037,7 @@ The MIPS Malta prototype board "malta"
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@item
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An ACER Pica "pica61"
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@item
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MIPS MIPSsim emulator pseudo board "mipssim"
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MIPS emulator pseudo board "mipssim"
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@end itemize
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|
||||
The generic emulation is supported by Debian 'Etch' and is able to
|
||||
|
|
@ -2085,7 +2085,9 @@ PC Keyboard
|
|||
IDE controller
|
||||
@end itemize
|
||||
|
||||
The MIPSsim emulation supports:
|
||||
The mipssim pseudo board emulation provides an environment similiar
|
||||
to what the proprietary MIPS emulator uses for running Linux.
|
||||
It supports:
|
||||
|
||||
@itemize @minus
|
||||
@item
|
||||
|
|
|
|||
Loading…
Reference in a new issue