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target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV

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Pointer mask is also affected by MPRV which means cur_pmbase/pmmask
should also take MPRV into consideration. As pointer mask for instruction
is not supported currently, so we can directly update cur_pmbase/pmmask
based on address related mode and xlen affected by MPRV now.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230614032547.35895-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-06-14 11:25:47 +08:00 committed by Alistair Francis
parent 3a610f5430
commit ef1ba32aff
2 changed files with 25 additions and 9 deletions
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7
target/riscv/cpu_helper.c
View file

@ -149,13 +149,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
void riscv_cpu_update_mask(CPURISCVState *env)
{
target_ulong mask = 0, base = 0;
RISCVMXL xl = env->xl;
/*
* TODO: Current RVJ spec does not specify
* how the extension interacts with XLEN.
*/
#ifndef CONFIG_USER_ONLY
int mode = cpu_address_mode(env);
xl = cpu_get_xl(env, mode);
if (riscv_has_ext(env, RVJ)) {
switch (env->priv) {
switch (mode) {
case PRV_M:
if (env->mmte & M_PM_ENABLE) {
mask = env->mpmmask;
@ -179,7 +182,7 @@ void riscv_cpu_update_mask(CPURISCVState *env)
}
}
#endif
if (env->xl == MXL_RV32) {
if (xl == MXL_RV32) {
env->cur_pmmask = mask & UINT32_MAX;
env->cur_pmbase = base & UINT32_MAX;
} else {

27
target/riscv/csr.c
View file

@ -1329,8 +1329,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
*/
if (env->debugger) {
env->xl = cpu_recompute_xl(env);
riscv_cpu_update_mask(env);
}
riscv_cpu_update_mask(env);
return RISCV_EXCP_NONE;
}
@ -3633,7 +3634,7 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmmask = val;
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmmask = val;
}
env->mmte |= EXT_STATUS_DIRTY;
@ -3661,8 +3662,11 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmmask = val;
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmmask = val;
if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
env->cur_pmmask &= UINT32_MAX;
}
}
env->mmte |= EXT_STATUS_DIRTY;
@ -3689,8 +3693,11 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmmask = val;
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmmask = val;
if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
env->cur_pmmask &= UINT32_MAX;
}
}
env->mmte |= EXT_STATUS_DIRTY;
@ -3713,7 +3720,7 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmbase = val;
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmbase = val;
}
env->mmte |= EXT_STATUS_DIRTY;
@ -3741,8 +3748,11 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmbase = val;
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmbase = val;
if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
env->cur_pmbase &= UINT32_MAX;
}
}
env->mmte |= EXT_STATUS_DIRTY;
@ -3769,8 +3779,11 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmbase = val;
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmbase = val;
if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
env->cur_pmbase &= UINT32_MAX;
}
}
env->mmte |= EXT_STATUS_DIRTY;