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target/microblaze: Convert mbar to decodetree
Split this out of the normal branch instructions, as it requires special handling. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -127,6 +127,8 @@ lwea 110010 ..... ..... ..... 0001 000 0000 @typea
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lwx 110010 ..... ..... ..... 1000 000 0000 @typea
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lwi 111010 ..... ..... ................ @typeb
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mbar 101110 imm:5 00010 0000 0000 0000 0100
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mul 010000 ..... ..... ..... 000 0000 0000 @typea
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mulh 010000 ..... ..... ..... 000 0000 0001 @typea
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mulhu 010000 ..... ..... ..... 000 0000 0011 @typea
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@ -1127,6 +1127,52 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg)
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return true;
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}
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static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
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{
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int mbar_imm = arg->imm;
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/* Data access memory barrier. */
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if ((mbar_imm & 2) == 0) {
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tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
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}
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/* Sleep. */
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if (mbar_imm & 16) {
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TCGv_i32 tmp_1;
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if (trap_userspace(dc, true)) {
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/* Sleep is a privileged instruction. */
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return true;
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}
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t_sync_flags(dc);
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tmp_1 = tcg_const_i32(1);
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tcg_gen_st_i32(tmp_1, cpu_env,
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-offsetof(MicroBlazeCPU, env)
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+offsetof(CPUState, halted));
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tcg_temp_free_i32(tmp_1);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
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gen_raise_exception(dc, EXCP_HLT);
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}
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/*
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* If !(mbar_imm & 1), this is an instruction access memory barrier
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* and we need to end the TB so that we recognize self-modified
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* code immediately.
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*
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* However, there are some data mbars that need the TB break
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* (and return to main loop) to recognize interrupts right away.
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* E.g. recognizing a change to an interrupt controller register.
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*
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* Therefore, choose to end the TB always.
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*/
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dc->cpustate_changed = 1;
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return true;
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}
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static bool trans_zero(DisasContext *dc, arg_zero *arg)
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{
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/* If opcode_0_illegal, trap. */
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@ -1417,50 +1463,13 @@ static void dec_bcc(DisasContext *dc)
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static void dec_br(DisasContext *dc)
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{
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unsigned int dslot, link, abs, mbar;
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unsigned int dslot, link, abs;
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uint32_t add_pc;
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dslot = dc->ir & (1 << 20);
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abs = dc->ir & (1 << 19);
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link = dc->ir & (1 << 18);
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/* Memory barrier. */
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mbar = (dc->ir >> 16) & 31;
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if (mbar == 2 && dc->imm == 4) {
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uint16_t mbar_imm = dc->rd;
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/* Data access memory barrier. */
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if ((mbar_imm & 2) == 0) {
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tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
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}
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/* mbar IMM & 16 decodes to sleep. */
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if (mbar_imm & 16) {
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TCGv_i32 tmp_1;
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if (trap_userspace(dc, true)) {
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/* Sleep is a privileged instruction. */
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return;
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}
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t_sync_flags(dc);
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tmp_1 = tcg_const_i32(1);
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tcg_gen_st_i32(tmp_1, cpu_env,
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-offsetof(MicroBlazeCPU, env)
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+offsetof(CPUState, halted));
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tcg_temp_free_i32(tmp_1);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
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gen_raise_exception(dc, EXCP_HLT);
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return;
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}
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/* Break the TB. */
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dc->cpustate_changed = 1;
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return;
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}
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if (dslot) {
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dec_setup_dslot(dc);
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}
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