mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
moved PCI init to BIOS - added ISA memory mapping registers and SMM support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2174 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
02a1602e62
commit
ee0ea1d0dd
1 changed files with 123 additions and 225 deletions
348
hw/piix_pci.c
348
hw/piix_pci.c
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@ -52,7 +52,123 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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return (irq_num + slot_addend) & 3;
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}
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PCIBus *i440fx_init(void)
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static uint32_t isa_page_descs[384 / 4];
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static uint8_t smm_enabled;
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static const uint32_t mar_addresses[15] = {
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0xa0000,
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0xc0000,
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0xc4000,
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0xc8000,
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0xcc000,
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0xd0000,
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0xd4000,
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0xd8000,
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0xdc000,
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0xe0000,
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0xe4000,
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0xe8000,
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0xec000,
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0xf0000,
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0x100000,
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};
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static void i440fx_update_memory_mappings(PCIDevice *d)
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{
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int i, r;
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uint32_t start, end, addr;
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uint32_t smram, smbase, smsize;
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for(i = 0; i < 14; i++) {
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r = (d->config[(i >> 1) + 0x61] >> ((i & 1) * 4)) & 3;
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start = mar_addresses[i];
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end = mar_addresses[i + 1];
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// printf("ISA mapping %08x: %d\n", start, r);
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switch(r) {
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case 3:
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/* RAM */
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cpu_register_physical_memory(start, end - start,
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start);
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break;
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case 2:
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/* ROM (XXX: not quite correct) */
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cpu_register_physical_memory(start, end - start,
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start | IO_MEM_ROM);
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break;
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case 1:
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case 0:
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/* XXX: should distinguish read/write cases */
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for(addr = start; addr < end; addr += 4096) {
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cpu_register_physical_memory(addr, 4096,
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isa_page_descs[(addr - 0xa0000) >> 12]);
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}
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break;
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}
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}
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smram = le32_to_cpu(*(uint32_t *)(d->config + 0x6c));
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if ((smm_enabled && (smram & 0x80000000)) || (smram & (1 << 26))) {
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/* Note: we assume the SMM area is in the 0xa0000-0x100000 range */
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smbase = (smram & 0xffff) << 16;
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smsize = (((smram >> 20) & 0xf) + 1) << 16;
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if (smbase >= 0xa0000 && (smbase + smsize) <= 0x100000) {
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cpu_register_physical_memory(smbase, smsize, smbase);
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}
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}
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}
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void i440fx_set_smm(PCIDevice *d, int val)
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{
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val = (val != 0);
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if (smm_enabled != val) {
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smm_enabled = val;
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i440fx_update_memory_mappings(d);
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}
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}
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/* XXX: suppress when better memory API. We make the assumption that
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no device (in particular the VGA) changes the memory mappings in
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the 0xa0000-0x100000 range */
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void i440fx_init_memory_mappings(PCIDevice *d)
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{
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int i;
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for(i = 0; i < 96; i++) {
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isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
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}
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}
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static void i440fx_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(d, address, val, len);
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if ((address >= 0x61 && address <= 0x67) || address == 0x6c)
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i440fx_update_memory_mappings(d);
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}
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static void i440fx_save(QEMUFile* f, void *opaque)
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{
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PCIDevice *d = opaque;
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pci_device_save(d, f);
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qemu_put_8s(f, &smm_enabled);
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}
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static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
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{
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PCIDevice *d = opaque;
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int ret;
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if (version_id != 1)
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return -EINVAL;
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ret = pci_device_load(d, f);
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if (ret < 0)
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return ret;
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i440fx_update_memory_mappings(d);
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qemu_get_8s(f, &smm_enabled);
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return 0;
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}
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PCIBus *i440fx_init(PCIDevice **pi440fx_state)
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{
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PCIBus *b;
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PCIDevice *d;
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@ -73,7 +189,7 @@ PCIBus *i440fx_init(void)
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register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
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d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
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NULL, NULL);
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NULL, i440fx_write_config);
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d->config[0x00] = 0x86; // vendor_id
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d->config[0x01] = 0x80;
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@ -83,6 +199,11 @@ PCIBus *i440fx_init(void)
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d->config[0x0a] = 0x00; // class_sub = host2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x00; // header_type
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d->config[0x6c] = 0x0a; /* SMRAM */
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register_savevm("I440FX", 0, 1, i440fx_save, i440fx_load, d);
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*pi440fx_state = d;
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return b;
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}
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@ -188,226 +309,3 @@ int piix3_init(PCIBus *bus)
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piix3_reset(d);
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return d->devfn;
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}
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/***********************************************************/
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/* XXX: the following should be moved to the PC BIOS */
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static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
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{
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return cpu_inb(NULL, addr);
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}
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static void isa_outb(uint32_t val, uint32_t addr)
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{
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cpu_outb(NULL, addr, val);
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}
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static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
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{
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return cpu_inw(NULL, addr);
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}
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static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
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{
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cpu_outw(NULL, addr, val);
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}
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static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
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{
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return cpu_inl(NULL, addr);
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}
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static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
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{
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cpu_outl(NULL, addr, val);
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}
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static uint32_t pci_bios_io_addr;
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static uint32_t pci_bios_mem_addr;
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/* host irqs corresponding to PCI irqs A-D */
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static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
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static int pci_bios_next_bus;
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static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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pci_data_write(s, addr, val, 4);
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}
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static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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pci_data_write(s, addr, val, 2);
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}
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static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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pci_data_write(s, addr, val, 1);
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}
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static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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return pci_data_read(s, addr, 4);
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}
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static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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return pci_data_read(s, addr, 2);
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}
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static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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return pci_data_read(s, addr, 1);
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}
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static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
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{
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PCIIORegion *r;
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uint16_t cmd;
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uint32_t ofs;
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if ( region_num == PCI_ROM_SLOT ) {
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ofs = 0x30;
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}else{
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ofs = 0x10 + region_num * 4;
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}
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pci_config_writel(d, ofs, addr);
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r = &d->io_regions[region_num];
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/* enable memory mappings */
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cmd = pci_config_readw(d, PCI_COMMAND);
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if ( region_num == PCI_ROM_SLOT )
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cmd |= 2;
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else if (r->type & PCI_ADDRESS_SPACE_IO)
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cmd |= 1;
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else
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cmd |= 2;
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pci_config_writew(d, PCI_COMMAND, cmd);
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}
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static void pci_bios_init_device(PCIDevice *d)
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{
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int class;
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PCIIORegion *r;
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uint32_t *paddr;
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int i, pin, pic_irq, vendor_id, device_id;
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class = pci_config_readw(d, PCI_CLASS_DEVICE);
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vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
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device_id = pci_config_readw(d, PCI_DEVICE_ID);
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switch(class) {
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case 0x0101:
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if (vendor_id == 0x8086 && device_id == 0x7010) {
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/* PIIX3 IDE */
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pci_config_writew(d, 0x40, 0x8000); // enable IDE0
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pci_config_writew(d, 0x42, 0x8000); // enable IDE1
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goto default_map;
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} else {
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/* IDE: we map it as in ISA mode */
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pci_set_io_region_addr(d, 0, 0x1f0);
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pci_set_io_region_addr(d, 1, 0x3f4);
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pci_set_io_region_addr(d, 2, 0x170);
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pci_set_io_region_addr(d, 3, 0x374);
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}
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break;
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case 0x0604:
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/* PCI to PCI bridge. Assign bus ID and recurse to configure
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devices on the secondary bus. */
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i = pci_bios_next_bus++;
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pci_config_writeb(d, 0x18, pci_bus_num(d->bus));
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pci_config_writeb(d, 0x19, i);
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pci_for_each_device(i, pci_bios_init_device);
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break;
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case 0x0300:
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if (vendor_id != 0x1234)
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goto default_map;
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/* VGA: map frame buffer to default Bochs VBE address */
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pci_set_io_region_addr(d, 0, 0xE0000000);
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break;
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case 0x0800:
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/* PIC */
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vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
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device_id = pci_config_readw(d, PCI_DEVICE_ID);
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if (vendor_id == 0x1014) {
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/* IBM */
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if (device_id == 0x0046 || device_id == 0xFFFF) {
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/* MPIC & MPIC2 */
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pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
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}
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}
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break;
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case 0xff00:
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if (vendor_id == 0x0106b &&
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(device_id == 0x0017 || device_id == 0x0022)) {
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/* macio bridge */
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pci_set_io_region_addr(d, 0, 0x80800000);
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}
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break;
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default:
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default_map:
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/* default memory mappings */
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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if (r->size) {
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if (r->type & PCI_ADDRESS_SPACE_IO)
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paddr = &pci_bios_io_addr;
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else
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paddr = &pci_bios_mem_addr;
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*paddr = (*paddr + r->size - 1) & ~(r->size - 1);
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pci_set_io_region_addr(d, i, *paddr);
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*paddr += r->size;
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}
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}
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break;
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}
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/* map the interrupt */
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pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
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if (pin != 0) {
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pin = pci_slot_get_pirq(d, pin - 1);
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pic_irq = pci_irqs[pin];
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pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
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}
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}
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/*
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* This function initializes the PCI devices as a normal PCI BIOS
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* would do. It is provided just in case the BIOS has no support for
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* PCI.
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*/
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void pci_bios_init(void)
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{
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int i, irq;
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uint8_t elcr[2];
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pci_bios_io_addr = 0xc000;
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pci_bios_mem_addr = 0xf0000000;
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/* activate IRQ mappings */
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elcr[0] = 0x00;
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elcr[1] = 0x00;
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for(i = 0; i < 4; i++) {
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irq = pci_irqs[i];
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/* set to trigger level */
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elcr[irq >> 3] |= (1 << (irq & 7));
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/* activate irq remapping in PIIX */
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pci_config_writeb(piix3_dev, 0x60 + i, irq);
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}
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isa_outb(elcr[0], 0x4d0);
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isa_outb(elcr[1], 0x4d1);
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pci_bios_next_bus = 1;
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pci_for_each_device(0, pci_bios_init_device);
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}
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