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s390x: Replace PAGE_SIZE, PAGE_SHIFT and PAGE_MASK
The PAGE_SIZE macro is causing trouble on Alpine Linux since it clashes with a macro from a system header there. We already have the TARGET_PAGE_SIZE, TARGET_PAGE_MASK and TARGET_PAGE_BITS macros in QEMU anyway, so let's simply replace the PAGE_SIZE, PAGE_MASK and PAGE_SHIFT macro with their TARGET_* counterparts. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/572 Message-Id: <20210901125800.611183-1-thuth@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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c35622387e
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4 changed files with 11 additions and 14 deletions
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@ -330,7 +330,7 @@ static unsigned int calc_sx(dma_addr_t ptr)
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static unsigned int calc_px(dma_addr_t ptr)
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{
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return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
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return ((unsigned long) ptr >> TARGET_PAGE_BITS) & ZPCI_PT_MASK;
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}
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static uint64_t get_rt_sto(uint64_t entry)
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@ -506,7 +506,7 @@ uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
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int8_t ett = 1;
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uint16_t error = 0;
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entry->iova = addr & PAGE_MASK;
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entry->iova = addr & TARGET_PAGE_MASK;
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entry->translated_addr = 0;
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entry->perm = IOMMU_RW;
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@ -526,7 +526,7 @@ static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr,
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{
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S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr);
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S390IOTLBEntry *entry;
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uint64_t iova = addr & PAGE_MASK;
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uint64_t iova = addr & TARGET_PAGE_MASK;
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uint16_t error = 0;
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IOMMUTLBEntry ret = {
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.target_as = &address_space_memory,
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@ -562,7 +562,7 @@ static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr,
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ret.perm = entry->perm;
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} else {
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ret.iova = iova;
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ret.addr_mask = ~PAGE_MASK;
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ret.addr_mask = ~TARGET_PAGE_MASK;
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ret.perm = IOMMU_NONE;
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}
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@ -868,7 +868,7 @@ static int s390_pci_msix_init(S390PCIBusDevice *pbdev)
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name = g_strdup_printf("msix-s390-%04x", pbdev->uid);
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memory_region_init_io(&pbdev->msix_notify_mr, OBJECT(pbdev),
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&s390_msi_ctrl_ops, pbdev, name, PAGE_SIZE);
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&s390_msi_ctrl_ops, pbdev, name, TARGET_PAGE_SIZE);
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memory_region_add_subregion(&pbdev->iommu->mr,
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pbdev->pci_group->zpci_group.msia,
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&pbdev->msix_notify_mr);
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@ -613,7 +613,7 @@ static uint32_t s390_pci_update_iotlb(S390PCIIOMMU *iommu,
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.iova = entry->iova,
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.translated_addr = entry->translated_addr,
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.perm = entry->perm,
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.addr_mask = ~PAGE_MASK,
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.addr_mask = ~TARGET_PAGE_MASK,
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},
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};
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@ -640,7 +640,7 @@ static uint32_t s390_pci_update_iotlb(S390PCIIOMMU *iommu,
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cache = g_new(S390IOTLBEntry, 1);
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cache->iova = entry->iova;
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cache->translated_addr = entry->translated_addr;
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cache->len = PAGE_SIZE;
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cache->len = TARGET_PAGE_SIZE;
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cache->perm = entry->perm;
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g_hash_table_replace(iommu->iotlb, &cache->iova, cache);
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dec_dma_avail(iommu);
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@ -725,8 +725,8 @@ int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
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while (entry.iova < start && entry.iova < end &&
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(dma_avail > 0 || entry.perm == IOMMU_NONE)) {
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dma_avail = s390_pci_update_iotlb(iommu, &entry);
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entry.iova += PAGE_SIZE;
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entry.translated_addr += PAGE_SIZE;
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entry.iova += TARGET_PAGE_SIZE;
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entry.translated_addr += TARGET_PAGE_SIZE;
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}
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}
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err:
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@ -51,7 +51,7 @@ static bool sccb_verify_boundary(uint64_t sccb_addr, uint16_t sccb_len,
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uint32_t code)
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{
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uint64_t sccb_max_addr = sccb_addr + sccb_len - 1;
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uint64_t sccb_boundary = (sccb_addr & PAGE_MASK) + PAGE_SIZE;
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uint64_t sccb_boundary = (sccb_addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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switch (code & SCLP_CMD_CODE_MASK) {
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case SCLP_CMDW_READ_SCP_INFO:
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@ -81,9 +81,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU)
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#define ZPCI_SDMA_ADDR 0x100000000ULL
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#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#define PAGE_DEFAULT_ACC 0
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#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
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@ -137,7 +134,7 @@ enum ZpciIoatDtype {
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#define ZPCI_TABLE_BITS 11
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#define ZPCI_PT_BITS 8
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#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
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#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + TARGET_PAGE_BITS)
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#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
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#define ZPCI_RTE_FLAG_MASK 0x3fffULL
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