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aspeed: add a max_ram_size property to the memory controller
This will be used to construct a memory region beyond the RAM region to let firmwares scan the address space with load/store to guess how much RAM the SoC has. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-7-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -31,6 +31,7 @@ static struct arm_boot_info aspeed_board_binfo = {
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typedef struct AspeedBoardState {
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AspeedSoCState soc;
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MemoryRegion ram;
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MemoryRegion max_ram;
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} AspeedBoardState;
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typedef struct AspeedBoardConfig {
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@ -127,6 +128,27 @@ static const AspeedBoardConfig aspeed_boards[] = {
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},
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};
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/*
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* The max ram region is for firmwares that scan the address space
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* with load/store to guess how much RAM the SoC has.
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*/
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static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
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{
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return 0;
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}
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static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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/* Discard writes */
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}
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static const MemoryRegionOps max_ram_ops = {
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.read = max_ram_read,
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.write = max_ram_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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#define FIRMWARE_ADDR 0x0
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static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
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@ -187,6 +209,7 @@ static void aspeed_board_init(MachineState *machine,
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AspeedBoardState *bmc;
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AspeedSoCClass *sc;
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DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
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ram_addr_t max_ram_size;
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bmc = g_new0(AspeedBoardState, 1);
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object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
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@ -226,6 +249,14 @@ static void aspeed_board_init(MachineState *machine,
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object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
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&error_abort);
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max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
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&error_abort);
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memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
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"max_ram", max_ram_size - ram_size);
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memory_region_add_subregion(get_system_memory(),
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sc->info->sdram_base + ram_size,
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&bmc->max_ram);
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aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
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aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
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@ -155,6 +155,8 @@ static void aspeed_soc_init(Object *obj)
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sc->info->silicon_rev);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size", &error_abort);
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object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
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"max-ram-size", &error_abort);
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for (i = 0; i < sc->info->wdts_num; i++) {
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object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
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@ -242,12 +242,14 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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s->ram_bits = ast2400_rambits(s);
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s->max_ram_size = 512 << 20;
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s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
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ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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s->ram_bits = ast2500_rambits(s);
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s->max_ram_size = 1024 << 20;
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s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
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ASPEED_SDMC_CACHE_INITIAL_DONE |
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@ -275,6 +277,7 @@ static const VMStateDescription vmstate_aspeed_sdmc = {
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static Property aspeed_sdmc_properties[] = {
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DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
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DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
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DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -27,6 +27,7 @@ typedef struct AspeedSDMCState {
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uint32_t silicon_rev;
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uint32_t ram_bits;
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uint64_t ram_size;
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uint64_t max_ram_size;
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uint32_t fixed_conf;
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} AspeedSDMCState;
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