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hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG

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Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-7-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Francisco Iglesias 2023-08-31 17:56:59 +01:00 committed by Peter Maydell
parent c6766f5b75
commit eadd3343c4
2 changed files with 178 additions and 0 deletions
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161
hw/misc/xlnx-versal-cframe-reg.c
View file

@ -569,6 +569,83 @@ static const MemoryRegionOps cframe_reg_fdri_ops = {
},
};
static uint64_t cframes_bcast_reg_read(void *opaque, hwaddr addr, unsigned size)
{
qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
HWADDR_PRIx "\n", __func__, addr);
return 0;
}
static void cframes_bcast_write(XlnxVersalCFrameBcastReg *s, uint8_t reg_addr,
uint32_t *wfifo)
{
XlnxCfiPacket pkt = {
.reg_addr = reg_addr,
.data[0] = wfifo[0],
.data[1] = wfifo[1],
.data[2] = wfifo[2],
.data[3] = wfifo[3]
};
for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
if (s->cfg.cframe[i]) {
xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt);
}
}
}
static void cframes_bcast_reg_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
uint32_t wfifo[WFIFO_SZ];
if (update_wfifo(addr, value, s->wfifo, wfifo)) {
uint8_t reg_addr = extract32(addr, 4, 6);
cframes_bcast_write(s, reg_addr, wfifo);
}
}
static uint64_t cframes_bcast_fdri_read(void *opaque, hwaddr addr,
unsigned size)
{
qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
HWADDR_PRIx "\n", __func__, addr);
return 0;
}
static void cframes_bcast_fdri_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
uint32_t wfifo[WFIFO_SZ];
if (update_wfifo(addr, value, s->wfifo, wfifo)) {
cframes_bcast_write(s, CFRAME_FDRI, wfifo);
}
}
static const MemoryRegionOps cframes_bcast_reg_reg_ops = {
.read = cframes_bcast_reg_read,
.write = cframes_bcast_reg_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static const MemoryRegionOps cframes_bcast_reg_fdri_ops = {
.read = cframes_bcast_fdri_read,
.write = cframes_bcast_fdri_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void cframe_reg_realize(DeviceState *dev, Error **errp)
{
XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(dev);
@ -663,6 +740,71 @@ static Property cframe_regs_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
static void cframe_bcast_reg_init(Object *obj)
{
XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem_reg, obj, &cframes_bcast_reg_reg_ops, s,
TYPE_XLNX_VERSAL_CFRAME_BCAST_REG, KEYHOLE_STREAM_4K);
memory_region_init_io(&s->iomem_fdri, obj, &cframes_bcast_reg_fdri_ops, s,
TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "-fdri",
KEYHOLE_STREAM_4K);
sysbus_init_mmio(sbd, &s->iomem_reg);
sysbus_init_mmio(sbd, &s->iomem_fdri);
}
static void cframe_bcast_reg_reset_enter(Object *obj, ResetType type)
{
XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(obj);
memset(s->wfifo, 0, WFIFO_SZ * sizeof(uint32_t));
}
static const VMStateDescription vmstate_cframe_bcast_reg = {
.name = TYPE_XLNX_VERSAL_CFRAME_BCAST_REG,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFrameBcastReg, 4),
VMSTATE_END_OF_LIST(),
}
};
static Property cframe_bcast_regs_props[] = {
DEFINE_PROP_LINK("cframe0", XlnxVersalCFrameBcastReg, cfg.cframe[0],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe1", XlnxVersalCFrameBcastReg, cfg.cframe[1],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe2", XlnxVersalCFrameBcastReg, cfg.cframe[2],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe3", XlnxVersalCFrameBcastReg, cfg.cframe[3],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe4", XlnxVersalCFrameBcastReg, cfg.cframe[4],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe5", XlnxVersalCFrameBcastReg, cfg.cframe[5],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe6", XlnxVersalCFrameBcastReg, cfg.cframe[6],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe7", XlnxVersalCFrameBcastReg, cfg.cframe[7],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe8", XlnxVersalCFrameBcastReg, cfg.cframe[8],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe9", XlnxVersalCFrameBcastReg, cfg.cframe[9],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe10", XlnxVersalCFrameBcastReg, cfg.cframe[10],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe11", XlnxVersalCFrameBcastReg, cfg.cframe[11],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe12", XlnxVersalCFrameBcastReg, cfg.cframe[12],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe13", XlnxVersalCFrameBcastReg, cfg.cframe[13],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_LINK("cframe14", XlnxVersalCFrameBcastReg, cfg.cframe[14],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
DEFINE_PROP_END_OF_LIST(),
};
static void cframe_reg_class_init(ObjectClass *klass, void *data)
{
ResettableClass *rc = RESETTABLE_CLASS(klass);
@ -677,6 +819,16 @@ static void cframe_reg_class_init(ObjectClass *klass, void *data)
xcic->cfi_transfer_packet = cframe_reg_cfi_transfer_packet;
}
static void cframe_bcast_reg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->vmsd = &vmstate_cframe_bcast_reg;
device_class_set_props(dc, cframe_bcast_regs_props);
rc->phases.enter = cframe_bcast_reg_reset_enter;
}
static const TypeInfo cframe_reg_info = {
.name = TYPE_XLNX_VERSAL_CFRAME_REG,
.parent = TYPE_SYS_BUS_DEVICE,
@ -689,9 +841,18 @@ static const TypeInfo cframe_reg_info = {
}
};
static const TypeInfo cframe_bcast_reg_info = {
.name = TYPE_XLNX_VERSAL_CFRAME_BCAST_REG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XlnxVersalCFrameBcastReg),
.class_init = cframe_bcast_reg_class_init,
.instance_init = cframe_bcast_reg_init,
};
static void cframe_reg_register_types(void)
{
type_register_static(&cframe_reg_info);
type_register_static(&cframe_bcast_reg_info);
}
type_init(cframe_reg_register_types)

17
include/hw/misc/xlnx-versal-cframe-reg.h
View file

@ -26,6 +26,10 @@
#define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx,cframe-reg"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameReg, XLNX_VERSAL_CFRAME_REG)
#define TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "xlnx.cframe-bcast-reg"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameBcastReg,
XLNX_VERSAL_CFRAME_BCAST_REG)
/*
* The registers in this module are 128 bits wide but it is ok to write
* and read them through 4 sequential 32 bit accesses (address[3:2] = 0,
@ -283,4 +287,17 @@ struct XlnxVersalCFrameReg {
bool row_configured;
};
struct XlnxVersalCFrameBcastReg {
SysBusDevice parent_obj;
MemoryRegion iomem_reg;
MemoryRegion iomem_fdri;
/* 128-bit wfifo. */
uint32_t wfifo[WFIFO_SZ];
struct {
XlnxCfiIf *cframe[15];
} cfg;
};
#endif