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target/mips: Move common helpers from helper.c to cpu.c
The rest of helper.c is TLB related. Extract the non TLB specific functions to cpu.c, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-6-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
2be565f9c2
commit
e9927723ba
3 changed files with 211 additions and 207 deletions
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@ -34,6 +34,215 @@
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#include "hw/semihosting/semihost.h"
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#include "qapi/qapi-commands-machine-target.h"
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#if !defined(CONFIG_USER_ONLY)
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/* Called for updates to CP0_Status. */
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = env->CP0_Status_rw_bitmask;
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target_ulong old = env->CP0_Status;
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if (env->insn_flags & ISA_MIPS_R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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#if defined(TARGET_MIPS64)
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uint32_t ksux = (1 << CP0St_KX) & val;
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ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
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ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
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val = (val & ~(7 << CP0St_UX)) | ksux;
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#endif
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if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
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}
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env->CP0_Status = (old & ~mask) | (val & mask);
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#if defined(TARGET_MIPS64)
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if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
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/* Access to at least one of the 64-bit segments has been disabled */
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tlb_flush(env_cpu(env));
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}
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#endif
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if (ase_mt_available(env)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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}
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = env->CP0_Cause;
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int i;
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if (env->insn_flags & ISA_MIPS_R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (env->insn_flags & ISA_MIPS_R6) {
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mask &= ~((1 << CP0Ca_WP) & val);
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}
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env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
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if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(env);
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} else {
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cpu_mips_start_count(env);
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}
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}
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/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_RESET] = "reset",
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[EXCP_SRESET] = "soft reset",
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[EXCP_DSS] = "debug single step",
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[EXCP_DINT] = "debug interrupt",
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[EXCP_NMI] = "non-maskable interrupt",
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[EXCP_MCHECK] = "machine check",
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[EXCP_EXT_INTERRUPT] = "interrupt",
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[EXCP_DFWATCH] = "deferred watchpoint",
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[EXCP_DIB] = "debug instruction breakpoint",
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[EXCP_IWATCH] = "instruction fetch watchpoint",
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[EXCP_AdEL] = "address error load",
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[EXCP_AdES] = "address error store",
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[EXCP_TLBF] = "TLB refill",
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[EXCP_IBE] = "instruction bus error",
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[EXCP_DBp] = "debug breakpoint",
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[EXCP_SYSCALL] = "syscall",
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[EXCP_BREAK] = "break",
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[EXCP_CpU] = "coprocessor unusable",
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[EXCP_RI] = "reserved instruction",
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[EXCP_OVERFLOW] = "arithmetic overflow",
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[EXCP_TRAP] = "trap",
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[EXCP_FPE] = "floating point",
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[EXCP_DDBS] = "debug data break store",
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[EXCP_DWATCH] = "data watchpoint",
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[EXCP_LTLBL] = "TLB modify",
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[EXCP_TLBL] = "TLB load",
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[EXCP_TLBS] = "TLB store",
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[EXCP_DBE] = "data bus error",
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[EXCP_DDBL] = "debug data break load",
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[EXCP_THREAD] = "thread",
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[EXCP_MDMX] = "MDMX",
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[EXCP_C2E] = "precise coprocessor 2",
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[EXCP_CACHE] = "cache error",
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[EXCP_TLBXI] = "TLB execute-inhibit",
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[EXCP_TLBRI] = "TLB read-inhibit",
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[EXCP_MSADIS] = "MSA disabled",
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[EXCP_MSAFPE] = "MSA floating point",
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};
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const char *mips_exception_name(int32_t exception)
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{
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if (exception < 0 || exception > EXCP_LAST) {
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return "unknown";
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}
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return excp_names[exception];
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}
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void cpu_set_exception_base(int vp_index, target_ulong address)
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{
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MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
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vp->env.exception_base = address;
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}
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target_ulong exception_resume_pc(CPUMIPSState *env)
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{
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target_ulong bad_pc;
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target_ulong isa_mode;
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isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
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bad_pc = env->active_tc.PC | isa_mode;
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/*
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* If the exception was raised from a delay slot, come back to
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* the jump.
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*/
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bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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}
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return bad_pc;
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}
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bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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if (cpu_mips_hw_interrupts_enabled(env) &&
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cpu_mips_hw_interrupts_pending(env)) {
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/* Raise it */
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cs->exception_index = EXCP_EXT_INTERRUPT;
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env->error_code = 0;
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mips_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
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uint32_t exception,
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int error_code,
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uintptr_t pc)
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{
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CPUState *cs = env_cpu(env);
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qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
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__func__, exception, mips_exception_name(exception),
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error_code);
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cs->exception_index = exception;
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env->error_code = error_code;
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cpu_loop_exit_restore(cs, pc);
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}
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static void mips_cpu_set_pc(CPUState *cs, vaddr value)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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@ -588,9 +797,3 @@ bool cpu_type_supports_cps_smp(const char *cpu_type)
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const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
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return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
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}
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void cpu_set_exception_base(int vp_index, target_ulong address)
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{
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MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
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vp->env.exception_base = address;
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}
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@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
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env->tlb->tlb_in_use = env->tlb->nb_tlb;
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}
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/* Called for updates to CP0_Status. */
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = env->CP0_Status_rw_bitmask;
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target_ulong old = env->CP0_Status;
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if (env->insn_flags & ISA_MIPS_R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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#if defined(TARGET_MIPS64)
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uint32_t ksux = (1 << CP0St_KX) & val;
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ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
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ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
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val = (val & ~(7 << CP0St_UX)) | ksux;
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#endif
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if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
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}
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env->CP0_Status = (old & ~mask) | (val & mask);
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#if defined(TARGET_MIPS64)
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if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
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/* Access to at least one of the 64-bit segments has been disabled */
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tlb_flush(env_cpu(env));
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}
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#endif
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if (ase_mt_available(env)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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}
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = env->CP0_Cause;
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int i;
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if (env->insn_flags & ISA_MIPS_R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (env->insn_flags & ISA_MIPS_R6) {
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mask &= ~((1 << CP0Ca_WP) & val);
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}
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env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
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if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(env);
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} else {
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cpu_mips_start_count(env);
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}
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}
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/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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@ -977,75 +878,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
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return physical;
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_RESET] = "reset",
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[EXCP_SRESET] = "soft reset",
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[EXCP_DSS] = "debug single step",
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[EXCP_DINT] = "debug interrupt",
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[EXCP_NMI] = "non-maskable interrupt",
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[EXCP_MCHECK] = "machine check",
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[EXCP_EXT_INTERRUPT] = "interrupt",
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[EXCP_DFWATCH] = "deferred watchpoint",
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[EXCP_DIB] = "debug instruction breakpoint",
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[EXCP_IWATCH] = "instruction fetch watchpoint",
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[EXCP_AdEL] = "address error load",
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[EXCP_AdES] = "address error store",
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[EXCP_TLBF] = "TLB refill",
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[EXCP_IBE] = "instruction bus error",
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[EXCP_DBp] = "debug breakpoint",
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[EXCP_SYSCALL] = "syscall",
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[EXCP_BREAK] = "break",
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[EXCP_CpU] = "coprocessor unusable",
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[EXCP_RI] = "reserved instruction",
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[EXCP_OVERFLOW] = "arithmetic overflow",
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[EXCP_TRAP] = "trap",
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[EXCP_FPE] = "floating point",
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[EXCP_DDBS] = "debug data break store",
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[EXCP_DWATCH] = "data watchpoint",
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[EXCP_LTLBL] = "TLB modify",
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[EXCP_TLBL] = "TLB load",
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[EXCP_TLBS] = "TLB store",
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[EXCP_DBE] = "data bus error",
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[EXCP_DDBL] = "debug data break load",
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[EXCP_THREAD] = "thread",
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[EXCP_MDMX] = "MDMX",
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[EXCP_C2E] = "precise coprocessor 2",
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[EXCP_CACHE] = "cache error",
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[EXCP_TLBXI] = "TLB execute-inhibit",
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[EXCP_TLBRI] = "TLB read-inhibit",
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[EXCP_MSADIS] = "MSA disabled",
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[EXCP_MSAFPE] = "MSA floating point",
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};
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static const char *mips_exception_name(int32_t exception)
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{
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if (exception < 0 || exception > EXCP_LAST) {
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return "unknown";
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}
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return excp_names[exception];
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}
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target_ulong exception_resume_pc(CPUMIPSState *env)
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{
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target_ulong bad_pc;
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target_ulong isa_mode;
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isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
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bad_pc = env->active_tc.PC | isa_mode;
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/*
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* If the exception was raised from a delay slot, come back to
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* the jump.
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*/
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bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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}
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return bad_pc;
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}
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#if !defined(CONFIG_USER_ONLY)
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static void set_hflags_for_handler(CPUMIPSState *env)
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{
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/* Exception handlers are entered in 32-bit mode. */
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@ -1400,24 +1233,6 @@ void mips_cpu_do_interrupt(CPUState *cs)
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cs->exception_index = EXCP_NONE;
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}
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bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
|
||||
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
if (cpu_mips_hw_interrupts_enabled(env) &&
|
||||
cpu_mips_hw_interrupts_pending(env)) {
|
||||
/* Raise it */
|
||||
cs->exception_index = EXCP_EXT_INTERRUPT;
|
||||
env->error_code = 0;
|
||||
mips_cpu_do_interrupt(cs);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
|
||||
{
|
||||
|
|
@ -1484,19 +1299,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
|
|||
}
|
||||
}
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
|
||||
uint32_t exception,
|
||||
int error_code,
|
||||
uintptr_t pc)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
|
||||
__func__, exception, mips_exception_name(exception),
|
||||
error_code);
|
||||
cs->exception_index = exception;
|
||||
env->error_code = error_code;
|
||||
|
||||
cpu_loop_exit_restore(cs, pc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -399,6 +399,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
|
|||
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
|
||||
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
|
||||
|
||||
const char *mips_exception_name(int32_t exception);
|
||||
|
||||
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
|
||||
int error_code, uintptr_t pc);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue