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pci: rename pci_register_bar_region() to pci_register_bar()

Browse source 
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-08 16:09:31 +03:00 committed by Anthony Liguori
parent 50181f10da
commit e824b2cc3b
29 changed files with 68 additions and 89 deletions
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5
hw/ac97.c
View file

@ -1316,9 +1316,8 @@ static int ac97_initfn (PCIDevice *dev)
memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
pci_register_bar_region (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
pci_register_bar_region (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO,
&s->io_nabm);
pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
qemu_register_reset (ac97_on_reset, s);
AUD_register_card ("ac97", &s->card);
ac97_on_reset (s);

5
hw/cirrus_vga.c
View file

@ -2948,10 +2948,9 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
/* memory #0 LFB */
/* memory #1 memory-mapped I/O */
/* XXX: s->vga.vram_size must be a power of two */
pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
&s->pci_bar);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
if (device_id == CIRRUS_ID_CLGD5446) {
pci_register_bar_region(&d->dev, 1, 0, &s->cirrus_mmio_io);
pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
}
return 0;
}

5
hw/e1000.c
View file

@ -1158,10 +1158,9 @@ static int pci_e1000_init(PCIDevice *pci_dev)
e1000_mmio_setup(d);
pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&d->mmio);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar_region(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
memmove(d->eeprom_data, e1000_eeprom_template,
sizeof e1000_eeprom_template);

7
hw/eepro100.c
View file

@ -1879,15 +1879,14 @@ static int e100_nic_init(PCIDevice *pci_dev)
/* Handler for memory-mapped I/O */
memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
PCI_MEM_SIZE);
pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
&s->mmio_bar);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
PCI_IO_SIZE);
pci_register_bar_region(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
/* FIXME: flash aliases to mmio?! */
memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
PCI_FLASH_SIZE);
pci_register_bar_region(&s->dev, 2, 0, &s->flash_bar);
pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));

2
hw/es1370.c
View file

@ -1009,7 +1009,7 @@ static int es1370_initfn (PCIDevice *dev)
c[PCI_MAX_LAT] = 0x80;
memory_region_init_io (&s->io, &es1370_io_ops, s, "es1370", 256);
pci_register_bar_region (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
qemu_register_reset (es1370_on_reset, s);
AUD_register_card ("es1370", &s->card);

14
hw/ide/cmd646.c
View file

@ -270,16 +270,12 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
setup_cmd646_bar(d, 0);
setup_cmd646_bar(d, 1);
pci_register_bar_region(dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
&d->cmd646_bar[0].data);
pci_register_bar_region(dev, 1, PCI_BASE_ADDRESS_SPACE_IO,
&d->cmd646_bar[0].cmd);
pci_register_bar_region(dev, 2, PCI_BASE_ADDRESS_SPACE_IO,
&d->cmd646_bar[1].data);
pci_register_bar_region(dev, 3, PCI_BASE_ADDRESS_SPACE_IO,
&d->cmd646_bar[1].cmd);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
bmdma_setup_bar(d);
pci_register_bar_region(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
/* TODO: RST# value should be 0 */
pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

2
hw/ide/ich.c
View file

@ -98,7 +98,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
msi_init(dev, 0x50, 1, true, false);
d->ahci.irq = d->card.irq[0];
pci_register_bar_region(&d->card, 5, 0, &d->ahci.mem);
pci_register_bar(&d->card, 5, 0, &d->ahci.mem);
return 0;
}

3
hw/ide/piix.c
View file

@ -155,8 +155,7 @@ static int pci_piix_ide_initfn(PCIDevice *dev)
qemu_register_reset(piix3_reset, d);
bmdma_setup_bar(d);
pci_register_bar_region(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO,
&d->bmdma_bar);
pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);

3
hw/ide/via.c
View file

@ -180,8 +180,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
qemu_register_reset(via_reset, d);
bmdma_setup_bar(d);
pci_register_bar_region(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO,
&d->bmdma_bar);
pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);

2
hw/intel-hda.c
View file

@ -1136,7 +1136,7 @@ static int intel_hda_init(PCIDevice *pci)
memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
"intel-hda", 0x4000);
pci_register_bar_region(&d->pci, 0, 0, &d->mmio);
pci_register_bar(&d->pci, 0, 0, &d->mmio);
if (d->msi) {
msi_init(&d->pci, 0x50, 1, true, false);
}

15
hw/ivshmem.c
View file

@ -336,7 +336,7 @@ static void create_shared_memory_BAR(IVShmemState *s, int fd) {
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
pci_register_bar_region(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
}
static void close_guest_eventfds(IVShmemState *s, int posn)
@ -543,9 +543,8 @@ static void ivshmem_setup_msi(IVShmemState * s) {
memory_region_init(&s->msix_bar, "ivshmem-msix", 4096);
if (!msix_init(&s->dev, s->vectors, &s->msix_bar, 1, 0)) {
pci_register_bar_region(&s->dev, 1,
PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->msix_bar);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->msix_bar);
IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
} else {
IVSHMEM_DPRINTF("msix initialization failed\n");
@ -665,8 +664,8 @@ static int pci_ivshmem_init(PCIDevice *dev)
}
/* region for registers*/
pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->ivshmem_mmio);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->ivshmem_mmio);
memory_region_init(&s->bar, "ivshmem-bar2-container", s->ivshmem_size);
@ -694,8 +693,8 @@ static int pci_ivshmem_init(PCIDevice *dev)
/* allocate/initialize space for interrupt handling */
s->peers = qemu_mallocz(s->nb_peers * sizeof(Peer));
pci_register_bar_region(&s->dev, 2,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ivshmem);
pci_register_bar(&s->dev, 2,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ivshmem);
s->eventfd_chr = qemu_mallocz(s->vectors * sizeof(CharDriverState *));

7
hw/lsi53c895a.c
View file

@ -2118,10 +2118,9 @@ static int lsi_scsi_init(PCIDevice *dev)
memory_region_init_io(&s->ram_io, &lsi_ram_ops, s, "lsi-ram", 0x2000);
memory_region_init_io(&s->io_io, &lsi_io_ops, s, "lsi-io", 256);
pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io);
pci_register_bar_region(&s->dev, 1, 0, &s->mmio_io);
pci_register_bar_region(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->ram_io);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io);
pci_register_bar(&s->dev, 1, 0, &s->mmio_io);
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
QTAILQ_INIT(&s->queue);
scsi_bus_new(&s->bus, &dev->qdev, 1, LSI_MAX_DEVS, &lsi_scsi_ops);

3
hw/macio.c
View file

@ -111,6 +111,5 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld,
d->config[0x3d] = 0x01; // interrupt on pin 1
macio_bar_setup(macio_state);
pci_register_bar_region(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&macio_state->bar);
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &macio_state->bar);
}

2
hw/ne2000.c
View file

@ -754,7 +754,7 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
s = &d->ne2000;
ne2000_setup_io(s, 0x100);
pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
s->irq = d->dev.irq[0];
qemu_macaddr_default_if_unset(&s->c.macaddr);

4
hw/openpic.c
View file

@ -1177,8 +1177,8 @@ qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
#endif
/* Register I/O spaces */
pci_register_bar_region(&opp->pci_dev, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY, &opp->mem);
pci_register_bar(&opp->pci_dev, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY, &opp->mem);
} else {
opp = qemu_mallocz(sizeof(openpic_t));
memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000);

6
hw/pci.c
View file

@ -881,8 +881,8 @@ static int pci_unregister_device(DeviceState *dev)
return 0;
}
void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
uint8_t type, MemoryRegion *memory)
void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint8_t type, MemoryRegion *memory)
{
PCIIORegion *r;
uint32_t addr;
@ -1956,7 +1956,7 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
qemu_put_ram_ptr(ptr);
pci_register_bar_region(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
return 0;
}

4
hw/pci.h
View file

@ -200,8 +200,8 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name,
PCIConfigReadFunc *config_read,
PCIConfigWriteFunc *config_write);
void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory);
void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory);
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,

4
hw/pcnet-pci.c
View file

@ -295,9 +295,9 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
memory_region_init_io(&d->io_bar, &pcnet_io_ops, d, "pcnet-io",
PCNET_IOPORT_SIZE);
pci_register_bar_region(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
pci_register_bar_region(pci_dev, 1, 0, &s->mmio);
pci_register_bar(pci_dev, 1, 0, &s->mmio);
s->irq = pci_dev->irq[0];
s->phys_mem_read = pci_physical_memory_read;

16
hw/qxl.c
View file

@ -1564,17 +1564,17 @@ static int qxl_init_common(PCIQXLDevice *qxl)
}
pci_register_bar_region(&qxl->pci, QXL_IO_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
pci_register_bar_region(&qxl->pci, QXL_ROM_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
pci_register_bar_region(&qxl->pci, QXL_RAM_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
pci_register_bar_region(&qxl->pci, QXL_VRAM_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
qxl->ssd.qxl.base.sif = &qxl_interface.base;
qxl->ssd.qxl.id = qxl->id;

6
hw/rtl8139.c
View file

@ -3471,10 +3471,8 @@ static int pci_rtl8139_init(PCIDevice *dev)
memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
&s->bar_io);
pci_register_bar_region(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->bar_mem);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
qemu_macaddr_default_if_unset(&s->conf.macaddr);

6
hw/sun4u.c
View file

@ -554,11 +554,9 @@ pci_ebus_init1(PCIDevice *pci_dev)
pci_dev->config[0x0D] = 0x0a; // latency_timer
isa_mmio_setup(&s->bar0, 0x1000000);
pci_register_bar_region(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->bar0);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
isa_mmio_setup(&s->bar1, 0x800000);
pci_register_bar_region(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->bar1);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
return 0;
}

2
hw/usb-ehci.c
View file

@ -2302,7 +2302,7 @@ static int usb_ehci_initfn(PCIDevice *dev)
qemu_register_reset(ehci_reset, s);
memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
fprintf(stderr, "*** EHCI support is under development ***\n");

2
hw/usb-ohci.c
View file

@ -1790,7 +1790,7 @@ static int usb_ohci_initfn_pci(struct PCIDevice *dev)
ohci->state.irq = ohci->pci_dev.irq[0];
/* TODO: avoid cast below by using dev */
pci_register_bar_region(&ohci->pci_dev, 0, 0, &ohci->state.mem);
pci_register_bar(&ohci->pci_dev, 0, 0, &ohci->state.mem);
return 0;
}

3
hw/usb-uhci.c
View file

@ -1159,8 +1159,7 @@ static int usb_uhci_common_initfn(PCIDevice *dev)
memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
/* Use region 4 for consistency with real hardware. BSD guests seem
to rely on this. */
pci_register_bar_region(&s->dev, 4,
PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
return 0;
}

3
hw/vga-pci.c
View file

@ -60,8 +60,7 @@ static int pci_vga_initfn(PCIDevice *dev)
s->screen_dump, s->text_update, s);
/* XXX: VGA_RAM_SIZE must be a power of two */
pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
&s->vram);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */

9
hw/virtio-pci.c
View file

@ -644,9 +644,8 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)
memory_region_init(&proxy->msix_bar, "virtio-msix", 4096);
if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors,
&proxy->msix_bar, 1, 0)) {
pci_register_bar_region(&proxy->pci_dev, 1,
PCI_BASE_ADDRESS_SPACE_MEMORY,
&proxy->msix_bar);
pci_register_bar(&proxy->pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
&proxy->msix_bar);
} else
vdev->nvectors = 0;
@ -658,8 +657,8 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)
memory_region_init_io(&proxy->bar, &virtio_pci_config_ops, proxy,
"virtio-pci", size);
pci_register_bar_region(&proxy->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
&proxy->bar);
pci_register_bar(&proxy->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
&proxy->bar);
if (!kvm_has_many_ioeventfds()) {
proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;

8
hw/vmware_vga.c
View file

@ -1291,13 +1291,13 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
"vmsvga-io", 0x10);
pci_register_bar_region(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
vmsvga_init(&s->chip, VGA_RAM_SIZE);
pci_register_bar_region(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
pci_register_bar_region(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
&s->chip.fifo_ram);
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
&s->chip.fifo_ram);
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */

2
hw/wdt_i6300esb.c
View file

@ -405,7 +405,7 @@ static int i6300esb_init(PCIDevice *dev)
d->previous_reboot_flag = 0;
memory_region_init_io(&d->io_mem, &i6300esb_ops, d, "i6300esb", 0x10);
pci_register_bar_region(&d->dev, 0, 0, &d->io_mem);
pci_register_bar(&d->dev, 0, 0, &d->io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
return 0;

7
hw/xen_platform.c
View file

@ -353,13 +353,12 @@ static int xen_platform_initfn(PCIDevice *dev)
pci_conf[PCI_INTERRUPT_PIN] = 1;
platform_ioport_bar_setup(d);
pci_register_bar_region(&d->pci_dev, 0,
PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
/* reserve 16MB mmio address for share memory*/
platform_mmio_setup(d);
pci_register_bar_region(&d->pci_dev, 1,
PCI_BASE_ADDRESS_MEM_PREFETCH, &d->mmio_bar);
pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
&d->mmio_bar);
platform_fixed_ioport_init(d);