mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-06 01:43:39 +00:00
Add new sane low-level memory accessors for PowerPC that do proper
size or zero extension, with homogenous names. Fix load & store strings: those are now endian-sensitive, by definition. Fix dcbz: must always align the target address to a cache line boundary. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3719 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
67d6abff60
commit
e7c240035f
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@ -22,9 +22,7 @@
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/* Memory load/store helpers */
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void glue(do_lsw, MEMSUFFIX) (int dst);
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void glue(do_lsw_le, MEMSUFFIX) (int dst);
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void glue(do_stsw, MEMSUFFIX) (int src);
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void glue(do_stsw_le, MEMSUFFIX) (int src);
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void glue(do_lmw, MEMSUFFIX) (int dst);
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void glue(do_lmw_le, MEMSUFFIX) (int dst);
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void glue(do_stmw, MEMSUFFIX) (int src);
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@ -39,9 +37,7 @@ void glue(do_POWER2_stfq_le, MEMSUFFIX) (void);
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#if defined(TARGET_PPC64)
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void glue(do_lsw_64, MEMSUFFIX) (int dst);
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void glue(do_lsw_le_64, MEMSUFFIX) (int dst);
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void glue(do_stsw_64, MEMSUFFIX) (int src);
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void glue(do_stsw_le_64, MEMSUFFIX) (int src);
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void glue(do_lmw_64, MEMSUFFIX) (int dst);
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void glue(do_lmw_le_64, MEMSUFFIX) (int dst);
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void glue(do_stmw_64, MEMSUFFIX) (int src);
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@ -18,27 +18,13 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "op_mem_access.h"
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/* Multiple word / string load and store */
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static always_inline target_ulong glue(ld32r, MEMSUFFIX) (target_ulong EA)
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(EA);
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return ((tmp & 0xFF000000UL) >> 24) | ((tmp & 0x00FF0000UL) >> 8) |
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((tmp & 0x0000FF00UL) << 8) | ((tmp & 0x000000FFUL) << 24);
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}
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static always_inline void glue(st32r, MEMSUFFIX) (target_ulong EA,
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target_ulong data)
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{
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uint32_t tmp =
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((data & 0xFF000000UL) >> 24) | ((data & 0x00FF0000UL) >> 8) |
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((data & 0x0000FF00UL) << 8) | ((data & 0x000000FFUL) << 24);
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glue(stl, MEMSUFFIX)(EA, tmp);
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}
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void glue(do_lmw, MEMSUFFIX) (int dst)
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{
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for (; dst < 32; dst++, T0 += 4) {
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env->gpr[dst] = glue(ldl, MEMSUFFIX)((uint32_t)T0);
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env->gpr[dst] = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
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}
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}
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@ -46,7 +32,7 @@ void glue(do_lmw, MEMSUFFIX) (int dst)
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void glue(do_lmw_64, MEMSUFFIX) (int dst)
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{
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for (; dst < 32; dst++, T0 += 4) {
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env->gpr[dst] = glue(ldl, MEMSUFFIX)((uint64_t)T0);
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env->gpr[dst] = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
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}
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}
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#endif
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@ -54,7 +40,7 @@ void glue(do_lmw_64, MEMSUFFIX) (int dst)
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void glue(do_stmw, MEMSUFFIX) (int src)
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{
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for (; src < 32; src++, T0 += 4) {
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glue(stl, MEMSUFFIX)((uint32_t)T0, env->gpr[src]);
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glue(st32, MEMSUFFIX)((uint32_t)T0, env->gpr[src]);
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}
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}
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@ -62,7 +48,7 @@ void glue(do_stmw, MEMSUFFIX) (int src)
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void glue(do_stmw_64, MEMSUFFIX) (int src)
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{
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for (; src < 32; src++, T0 += 4) {
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glue(stl, MEMSUFFIX)((uint64_t)T0, env->gpr[src]);
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glue(st32, MEMSUFFIX)((uint64_t)T0, env->gpr[src]);
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}
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}
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#endif
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@ -70,7 +56,7 @@ void glue(do_stmw_64, MEMSUFFIX) (int src)
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void glue(do_lmw_le, MEMSUFFIX) (int dst)
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{
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for (; dst < 32; dst++, T0 += 4) {
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env->gpr[dst] = glue(ld32r, MEMSUFFIX)((uint32_t)T0);
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env->gpr[dst] = glue(ldu32r, MEMSUFFIX)((uint32_t)T0);
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}
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}
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@ -78,7 +64,7 @@ void glue(do_lmw_le, MEMSUFFIX) (int dst)
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void glue(do_lmw_le_64, MEMSUFFIX) (int dst)
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{
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for (; dst < 32; dst++, T0 += 4) {
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env->gpr[dst] = glue(ld32r, MEMSUFFIX)((uint64_t)T0);
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env->gpr[dst] = glue(ldu32r, MEMSUFFIX)((uint64_t)T0);
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}
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}
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#endif
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@ -105,14 +91,14 @@ void glue(do_lsw, MEMSUFFIX) (int dst)
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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env->gpr[dst++] = glue(ldl, MEMSUFFIX)((uint32_t)T0);
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env->gpr[dst++] = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
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if (unlikely(dst == 32))
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dst = 0;
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}
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if (unlikely(T1 != 0)) {
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tmp = 0;
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
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tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh;
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tmp |= glue(ldu8, MEMSUFFIX)((uint32_t)T0) << sh;
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}
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env->gpr[dst] = tmp;
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}
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@ -125,14 +111,14 @@ void glue(do_lsw_64, MEMSUFFIX) (int dst)
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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env->gpr[dst++] = glue(ldl, MEMSUFFIX)((uint64_t)T0);
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env->gpr[dst++] = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
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if (unlikely(dst == 32))
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dst = 0;
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}
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if (unlikely(T1 != 0)) {
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tmp = 0;
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
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tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh;
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tmp |= glue(ldu8, MEMSUFFIX)((uint64_t)T0) << sh;
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}
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env->gpr[dst] = tmp;
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}
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@ -144,13 +130,13 @@ void glue(do_stsw, MEMSUFFIX) (int src)
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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glue(stl, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]);
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glue(st32, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]);
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if (unlikely(src == 32))
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src = 0;
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}
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if (unlikely(T1 != 0)) {
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
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glue(stb, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
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glue(st8, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
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}
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}
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@ -160,85 +146,13 @@ void glue(do_stsw_64, MEMSUFFIX) (int src)
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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glue(stl, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]);
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glue(st32, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]);
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if (unlikely(src == 32))
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src = 0;
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}
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if (unlikely(T1 != 0)) {
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
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glue(stb, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
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}
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}
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#endif
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void glue(do_lsw_le, MEMSUFFIX) (int dst)
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{
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uint32_t tmp;
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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env->gpr[dst++] = glue(ld32r, MEMSUFFIX)((uint32_t)T0);
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if (unlikely(dst == 32))
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dst = 0;
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}
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if (unlikely(T1 != 0)) {
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tmp = 0;
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) {
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tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh;
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}
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env->gpr[dst] = tmp;
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}
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}
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#if defined(TARGET_PPC64)
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void glue(do_lsw_le_64, MEMSUFFIX) (int dst)
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{
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uint32_t tmp;
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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env->gpr[dst++] = glue(ld32r, MEMSUFFIX)((uint64_t)T0);
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if (unlikely(dst == 32))
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dst = 0;
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}
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if (unlikely(T1 != 0)) {
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tmp = 0;
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) {
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tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh;
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}
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env->gpr[dst] = tmp;
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}
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}
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#endif
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void glue(do_stsw_le, MEMSUFFIX) (int src)
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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glue(st32r, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]);
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if (unlikely(src == 32))
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src = 0;
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}
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if (unlikely(T1 != 0)) {
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8)
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glue(stb, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
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}
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}
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#if defined(TARGET_PPC64)
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void glue(do_stsw_le_64, MEMSUFFIX) (int src)
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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glue(st32r, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]);
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if (unlikely(src == 32))
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src = 0;
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}
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if (unlikely(T1 != 0)) {
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8)
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glue(stb, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
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glue(st8, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
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}
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}
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#endif
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@ -281,6 +195,7 @@ void glue(do_dcbz, MEMSUFFIX) (void)
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/* XXX: should be 970 specific (?) */
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if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
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dcache_line_size = 32;
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T0 &= ~(uint32_t)(dcache_line_size - 1);
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
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@ -327,6 +242,7 @@ void glue(do_dcbz_64, MEMSUFFIX) (void)
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/* XXX: should be 970 specific (?) */
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if (((env->spr[SPR_970_HID5] >> 6) & 0x3) == 0x2)
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dcache_line_size = 32;
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T0 &= ~(uint64_t)(dcache_line_size - 1);
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glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
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glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
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glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
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@ -375,7 +291,7 @@ void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
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d = 24;
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reg = dest;
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for (i = 0; i < T1; i++) {
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c = glue(ldub, MEMSUFFIX)((uint32_t)T0++);
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c = glue(ldu8, MEMSUFFIX)((uint32_t)T0++);
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/* ra (if not 0) and rb are never modified */
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if (likely(reg != rb && (ra == 0 || reg != ra))) {
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env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
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@ -408,14 +324,7 @@ static always_inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA)
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} u;
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u.d = glue(ldfq, MEMSUFFIX)(EA);
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u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
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((u.u & 0x00FF000000000000ULL) >> 40) |
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((u.u & 0x0000FF0000000000ULL) >> 24) |
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((u.u & 0x000000FF00000000ULL) >> 8) |
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((u.u & 0x00000000FF000000ULL) << 8) |
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((u.u & 0x0000000000FF0000ULL) << 24) |
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((u.u & 0x000000000000FF00ULL) << 40) |
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((u.u & 0x00000000000000FFULL) << 56);
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u.u = bswap64(u.u);
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return u.d;
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}
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@ -440,14 +349,7 @@ static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d)
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} u;
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u.d = d;
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u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
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((u.u & 0x00FF000000000000ULL) >> 40) |
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((u.u & 0x0000FF0000000000ULL) >> 24) |
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((u.u & 0x000000FF00000000ULL) >> 8) |
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((u.u & 0x00000000FF000000ULL) << 8) |
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((u.u & 0x0000000000FF0000ULL) << 24) |
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((u.u & 0x000000000000FF00ULL) << 40) |
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((u.u & 0x00000000000000FFULL) << 56);
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u.u = bswap64(u.u);
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glue(stfq, MEMSUFFIX)(EA, u.d);
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}
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File diff suppressed because it is too large
Load diff
148
target-ppc/op_mem_access.h
Normal file
148
target-ppc/op_mem_access.h
Normal file
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@ -0,0 +1,148 @@
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/*
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* PowerPC emulation memory access helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
|
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
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* Lesser General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU Lesser General Public
|
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* License along with this library; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* 8 bits accesses */
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static always_inline target_ulong glue(ldu8, MEMSUFFIX) (target_ulong EA)
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{
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return (uint8_t)glue(ldub, MEMSUFFIX)(EA);
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}
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static always_inline target_long glue(lds8, MEMSUFFIX) (target_ulong EA)
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{
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return (int8_t)glue(ldsb, MEMSUFFIX)(EA);
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}
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static always_inline void glue(st8, MEMSUFFIX) (target_ulong EA, uint8_t val)
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{
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glue(stb, MEMSUFFIX)(EA, val);
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}
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/* 16 bits accesses */
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static always_inline target_ulong glue(ldu16, MEMSUFFIX) (target_ulong EA)
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{
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return (uint16_t)glue(lduw, MEMSUFFIX)(EA);
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}
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static always_inline target_long glue(lds16, MEMSUFFIX) (target_ulong EA)
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{
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return (int16_t)glue(ldsw, MEMSUFFIX)(EA);
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}
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static always_inline void glue(st16, MEMSUFFIX) (target_ulong EA, uint16_t val)
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{
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glue(stw, MEMSUFFIX)(EA, val);
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}
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static always_inline target_ulong glue(ldu16r, MEMSUFFIX) (target_ulong EA)
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{
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return (uint16_t)bswap16(glue(lduw, MEMSUFFIX)(EA));
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}
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static always_inline target_long glue(lds16r, MEMSUFFIX) (target_ulong EA)
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{
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return (int16_t)bswap16(glue(lduw, MEMSUFFIX)(EA));
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}
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static always_inline void glue(st16r, MEMSUFFIX) (target_ulong EA, uint16_t val)
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{
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glue(stw, MEMSUFFIX)(EA, bswap16(val));
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}
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/* 32 bits accesses */
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static always_inline uint32_t glue(__ldul, MEMSUFFIX) (target_ulong EA)
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{
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return (uint32_t)glue(ldl, MEMSUFFIX)(EA);
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}
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static always_inline int32_t glue(__ldsl, MEMSUFFIX) (target_ulong EA)
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{
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return (int32_t)glue(ldl, MEMSUFFIX)(EA);
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}
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static always_inline target_ulong glue(ldu32, MEMSUFFIX) (target_ulong EA)
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{
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return glue(__ldul, MEMSUFFIX)(EA);
|
||||
}
|
||||
|
||||
static always_inline target_long glue(lds32, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return glue(__ldsl, MEMSUFFIX)(EA);
|
||||
}
|
||||
|
||||
static always_inline void glue(st32, MEMSUFFIX) (target_ulong EA, uint32_t val)
|
||||
{
|
||||
glue(stl, MEMSUFFIX)(EA, val);
|
||||
}
|
||||
|
||||
static always_inline target_ulong glue(ldu32r, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return bswap32(glue(__ldul, MEMSUFFIX)(EA));
|
||||
}
|
||||
|
||||
static always_inline target_long glue(lds32r, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return (int32_t)bswap32(glue(__ldul, MEMSUFFIX)(EA));
|
||||
}
|
||||
|
||||
static always_inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t val)
|
||||
{
|
||||
glue(stl, MEMSUFFIX)(EA, bswap32(val));
|
||||
}
|
||||
|
||||
/* 64 bits accesses */
|
||||
static always_inline uint64_t glue(__lduq, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return (uint64_t)glue(ldq, MEMSUFFIX)(EA);
|
||||
}
|
||||
|
||||
static always_inline int64_t glue(__ldsq, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return (int64_t)glue(ldq, MEMSUFFIX)(EA);
|
||||
}
|
||||
|
||||
static always_inline uint64_t glue(ldu64, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return glue(__lduq, MEMSUFFIX)(EA);
|
||||
}
|
||||
|
||||
static always_inline int64_t glue(lds64, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return glue(__ldsq, MEMSUFFIX)(EA);
|
||||
}
|
||||
|
||||
static always_inline void glue(st64, MEMSUFFIX) (target_ulong EA, uint64_t val)
|
||||
{
|
||||
glue(stq, MEMSUFFIX)(EA, val);
|
||||
}
|
||||
|
||||
static always_inline uint64_t glue(ldu64r, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return bswap64(glue(__lduq, MEMSUFFIX)(EA));
|
||||
}
|
||||
|
||||
static always_inline int64_t glue(lds64r, MEMSUFFIX) (target_ulong EA)
|
||||
{
|
||||
return (int64_t)bswap64(glue(__lduq, MEMSUFFIX)(EA));
|
||||
}
|
||||
|
||||
static always_inline void glue(st64r, MEMSUFFIX) (target_ulong EA, uint64_t val)
|
||||
{
|
||||
glue(stq, MEMSUFFIX)(EA, bswap64(val));
|
||||
}
|
||||
|
|
@ -2455,12 +2455,37 @@ GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
|
|||
/*** Integer load and store strings ***/
|
||||
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
|
||||
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
|
||||
/* string load & stores are by definition endian-safe */
|
||||
#define gen_op_lswi_le_raw gen_op_lswi_raw
|
||||
#define gen_op_lswi_le_user gen_op_lswi_user
|
||||
#define gen_op_lswi_le_kernel gen_op_lswi_kernel
|
||||
#define gen_op_lswi_le_hypv gen_op_lswi_hypv
|
||||
#define gen_op_lswi_le_64_raw gen_op_lswi_raw
|
||||
#define gen_op_lswi_le_64_user gen_op_lswi_user
|
||||
#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
|
||||
#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
|
||||
static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
|
||||
GEN_MEM_FUNCS(lswi),
|
||||
};
|
||||
#define gen_op_lswx_le_raw gen_op_lswx_raw
|
||||
#define gen_op_lswx_le_user gen_op_lswx_user
|
||||
#define gen_op_lswx_le_kernel gen_op_lswx_kernel
|
||||
#define gen_op_lswx_le_hypv gen_op_lswx_hypv
|
||||
#define gen_op_lswx_le_64_raw gen_op_lswx_raw
|
||||
#define gen_op_lswx_le_64_user gen_op_lswx_user
|
||||
#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
|
||||
#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
|
||||
static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
|
||||
GEN_MEM_FUNCS(lswx),
|
||||
};
|
||||
#define gen_op_stsw_le_raw gen_op_stsw_raw
|
||||
#define gen_op_stsw_le_user gen_op_stsw_user
|
||||
#define gen_op_stsw_le_kernel gen_op_stsw_kernel
|
||||
#define gen_op_stsw_le_hypv gen_op_stsw_hypv
|
||||
#define gen_op_stsw_le_64_raw gen_op_stsw_raw
|
||||
#define gen_op_stsw_le_64_user gen_op_stsw_user
|
||||
#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
|
||||
#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
|
||||
static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
|
||||
GEN_MEM_FUNCS(stsw),
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue