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target/loongarch: Support LoongArch32 TLB entry
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn> Message-Id: <20230822071405.35386-2-philmd@linaro.org>
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@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
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FIELD(TLBENTRY, PLV, 2, 2)
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FIELD(TLBENTRY, MAT, 4, 2)
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FIELD(TLBENTRY, G, 6, 1)
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FIELD(TLBENTRY, PPN, 12, 36)
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FIELD(TLBENTRY, NR, 61, 1)
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FIELD(TLBENTRY, NX, 62, 1)
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FIELD(TLBENTRY, RPLV, 63, 1)
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FIELD(TLBENTRY_32, PPN, 8, 24)
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FIELD(TLBENTRY_64, PPN, 12, 36)
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FIELD(TLBENTRY_64, NR, 61, 1)
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FIELD(TLBENTRY_64, NX, 62, 1)
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FIELD(TLBENTRY_64, RPLV, 63, 1)
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#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
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FIELD(CSR_ASID, ASID, 0, 10)
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@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
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tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
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tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
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tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
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tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
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tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
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tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
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tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
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if (is_la64(env)) {
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tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
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tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
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tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
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tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
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} else {
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tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
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tlb_nx = 0;
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tlb_nr = 0;
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tlb_rplv = 0;
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}
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/* Check access rights */
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if (!tlb_v) {
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@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
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* tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
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* need adjust.
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*/
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*physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
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*physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
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(address & MAKE_64BIT_MASK(0, tlb_ps));
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*prot = PAGE_READ;
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if (tlb_d) {
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