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https://gitlab.com/qemu-project/qemu
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tcg-ia64: Use TCGMemOp within qemu_ldst routines
Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
5c5432e7d6
commit
e3afa1c4ad
1 changed files with 91 additions and 82 deletions
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@ -1496,7 +1496,7 @@ static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
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R2 is loaded with the address of the addend TLB entry.
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R57 is loaded with the address, zero extented on 32-bit targets. */
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static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
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int s_bits, uint64_t offset_rw,
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TCGMemOp s_bits, uint64_t offset_rw,
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uint64_t offset_addend)
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{
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tcg_out_bundle(s, mII,
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@ -1538,23 +1538,24 @@ static const void * const qemu_ld_helpers[4] = {
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helper_ldq_mmu,
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};
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static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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TCGMemOp opc)
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{
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int addr_reg, data_reg, mem_index, s_bits, bswap;
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uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
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uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
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OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
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static const uint64_t opc_ld_m1[4] = {
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OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
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};
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static const uint64_t opc_ext_i29[8] = {
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OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
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OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
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};
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int addr_reg, data_reg, mem_index;
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TCGMemOp s_bits, bswap;
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data_reg = *args++;
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addr_reg = *args++;
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mem_index = *args;
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s_bits = opc & 3;
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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s_bits = opc & MO_SIZE;
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bswap = opc & MO_BSWAP;
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/* Read the TLB entry */
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tcg_out_qemu_tlb(s, addr_reg, s_bits,
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@ -1575,14 +1576,14 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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TCG_REG_R3, TCG_REG_R57),
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tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
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TCG_REG_R3, 0));
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if (bswap && s_bits == 1) {
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if (bswap && s_bits == MO_16) {
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tcg_out_bundle(s, MmI,
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tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
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TCG_REG_R8, TCG_REG_R3),
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
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tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
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TCG_REG_R8, TCG_REG_R8, 15, 15));
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} else if (bswap && s_bits == 2) {
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} else if (bswap && s_bits == MO_32) {
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tcg_out_bundle(s, MmI,
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tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
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TCG_REG_R8, TCG_REG_R3),
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@ -1596,7 +1597,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
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}
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if (!bswap || s_bits == 0) {
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if (!bswap) {
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tcg_out_bundle(s, miB,
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tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
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mem_index, TCG_REG_R0),
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@ -1613,7 +1614,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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TCG_REG_B0, TCG_REG_B6));
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}
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if (opc == 3) {
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if (s_bits == MO_64) {
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tcg_out_bundle(s, miI,
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
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@ -1623,7 +1624,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_bundle(s, miI,
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
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tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc],
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tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE],
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data_reg, TCG_REG_R8));
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}
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}
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@ -1637,22 +1638,21 @@ static const void * const qemu_st_helpers[4] = {
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helper_stq_mmu,
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};
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static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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TCGMemOp opc)
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{
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int addr_reg, data_reg, mem_index, bswap;
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uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
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static const uint64_t opc_st_m4[4] = {
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OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
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};
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int addr_reg, data_reg, mem_index;
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TCGMemOp s_bits;
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data_reg = *args++;
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addr_reg = *args++;
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mem_index = *args;
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s_bits = opc & MO_SIZE;
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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tcg_out_qemu_tlb(s, addr_reg, opc,
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tcg_out_qemu_tlb(s, addr_reg, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
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offsetof(CPUArchState, tlb_table[mem_index][0].addend));
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@ -1660,9 +1660,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_bundle(s, mLX,
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tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
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TCG_REG_R56, 0, TCG_AREG0),
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tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
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tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]),
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tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
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(tcg_target_long) qemu_st_helpers[opc]));
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(tcg_target_long) qemu_st_helpers[s_bits]));
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tcg_out_bundle(s, MmI,
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tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
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TCG_REG_R2, 8),
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@ -1671,14 +1671,20 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
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TCG_REG_R3, 0));
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if (!bswap || opc == 0) {
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switch (opc) {
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case MO_8:
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case MO_16:
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case MO_32:
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case MO_64:
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tcg_out_bundle(s, mii,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
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0, data_reg),
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
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} else if (opc == 1) {
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break;
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case MO_16 | MO_BSWAP:
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tcg_out_bundle(s, miI,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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@ -1692,7 +1698,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
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TCG_REG_R2, TCG_REG_R2, 0xb));
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data_reg = TCG_REG_R2;
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} else if (opc == 2) {
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break;
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case MO_32 | MO_BSWAP:
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tcg_out_bundle(s, miI,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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@ -1706,7 +1714,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
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TCG_REG_R2, TCG_REG_R2, 0xb));
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data_reg = TCG_REG_R2;
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} else if (opc == 3) {
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break;
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case MO_64 | MO_BSWAP:
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tcg_out_bundle(s, miI,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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@ -1715,10 +1725,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
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TCG_REG_R2, data_reg, 0xb));
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data_reg = TCG_REG_R2;
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break;
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default:
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tcg_abort();
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}
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tcg_out_bundle(s, miB,
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tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
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tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
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data_reg, TCG_REG_R3),
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tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
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mem_index, TCG_REG_R0),
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@ -1728,7 +1742,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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#else /* !CONFIG_SOFTMMU */
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static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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TCGMemOp opc)
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{
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static uint64_t const opc_ld_m1[4] = {
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OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
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@ -1736,17 +1751,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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static uint64_t const opc_sxt_i29[4] = {
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OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
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};
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int addr_reg, data_reg, s_bits, bswap;
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int addr_reg, data_reg;
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TCGMemOp s_bits, bswap;
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data_reg = *args++;
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addr_reg = *args++;
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s_bits = opc & 3;
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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s_bits = opc & MO_SIZE;
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bswap = opc & MO_BSWAP;
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#if TARGET_LONG_BITS == 32
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if (GUEST_BASE != 0) {
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@ -1764,8 +1775,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
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}
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if (!bswap || s_bits == 0) {
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if (s_bits == opc) {
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if (!bswap) {
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if (!(opc & MO_SIGN)) {
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tcg_out_bundle(s, miI,
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tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
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data_reg, TCG_REG_R2),
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@ -1779,7 +1790,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
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data_reg, data_reg));
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}
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} else if (s_bits == 3) {
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} else if (s_bits == MO_64) {
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tcg_out_bundle(s, mII,
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tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
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data_reg, TCG_REG_R2),
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@ -1787,7 +1798,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
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data_reg, data_reg, 0xb));
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} else {
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if (s_bits == 1) {
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if (s_bits == MO_16) {
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tcg_out_bundle(s, mII,
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tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
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data_reg, TCG_REG_R2),
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@ -1802,7 +1813,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
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data_reg, data_reg, 31, 31));
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}
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if (opc == s_bits) {
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if (!(opc & MO_SIGN)) {
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tcg_out_bundle(s, miI,
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
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@ -1833,28 +1844,28 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
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}
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if (bswap && s_bits == 1) {
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if (bswap && s_bits == MO_16) {
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tcg_out_bundle(s, mII,
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
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data_reg, data_reg, 15, 15),
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tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
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data_reg, data_reg, 0xb));
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} else if (bswap && s_bits == 2) {
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} else if (bswap && s_bits == MO_32) {
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tcg_out_bundle(s, mII,
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
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data_reg, data_reg, 31, 31),
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tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
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data_reg, data_reg, 0xb));
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} else if (bswap && s_bits == 3) {
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} else if (bswap && s_bits == MO_64) {
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tcg_out_bundle(s, miI,
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
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tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
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data_reg, data_reg, 0xb));
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}
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if (s_bits != opc) {
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if (opc & MO_SIGN) {
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tcg_out_bundle(s, miI,
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
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@ -1864,24 +1875,22 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#endif
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}
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static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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TCGMemOp opc)
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{
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static uint64_t const opc_st_m4[4] = {
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OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
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};
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int addr_reg, data_reg, bswap;
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int addr_reg, data_reg;
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#if TARGET_LONG_BITS == 64
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uint64_t add_guest_base;
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#endif
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TCGMemOp s_bits, bswap;
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data_reg = *args++;
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addr_reg = *args++;
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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s_bits = opc & MO_SIZE;
|
||||
bswap = opc & MO_BSWAP;
|
||||
|
||||
#if TARGET_LONG_BITS == 32
|
||||
if (GUEST_BASE != 0) {
|
||||
|
|
@ -1900,7 +1909,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
}
|
||||
|
||||
if (bswap) {
|
||||
if (opc == 1) {
|
||||
if (s_bits == MO_16) {
|
||||
tcg_out_bundle(s, mII,
|
||||
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
||||
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
|
||||
|
|
@ -1908,7 +1917,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
|
||||
TCG_REG_R3, TCG_REG_R3, 0xb));
|
||||
data_reg = TCG_REG_R3;
|
||||
} else if (opc == 2) {
|
||||
} else if (s_bits == MO_32) {
|
||||
tcg_out_bundle(s, mII,
|
||||
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
||||
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
|
||||
|
|
@ -1916,7 +1925,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
|
||||
TCG_REG_R3, TCG_REG_R3, 0xb));
|
||||
data_reg = TCG_REG_R3;
|
||||
} else if (opc == 3) {
|
||||
} else if (s_bits == MO_64) {
|
||||
tcg_out_bundle(s, miI,
|
||||
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
||||
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
||||
|
|
@ -1926,7 +1935,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
}
|
||||
}
|
||||
tcg_out_bundle(s, mmI,
|
||||
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
|
||||
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
|
||||
data_reg, TCG_REG_R2),
|
||||
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
||||
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
||||
|
|
@ -1939,14 +1948,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
||||
}
|
||||
|
||||
if (!bswap || opc == 0) {
|
||||
if (!bswap) {
|
||||
tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
|
||||
add_guest_base,
|
||||
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
|
||||
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
|
||||
data_reg, addr_reg),
|
||||
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
||||
} else {
|
||||
if (opc == 1) {
|
||||
if (s_bits == MO_16) {
|
||||
tcg_out_bundle(s, mII,
|
||||
add_guest_base,
|
||||
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
|
||||
|
|
@ -1954,7 +1963,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
|
||||
TCG_REG_R3, TCG_REG_R3, 0xb));
|
||||
data_reg = TCG_REG_R3;
|
||||
} else if (opc == 2) {
|
||||
} else if (s_bits == MO_32) {
|
||||
tcg_out_bundle(s, mII,
|
||||
add_guest_base,
|
||||
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
|
||||
|
|
@ -1962,7 +1971,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
|
||||
TCG_REG_R3, TCG_REG_R3, 0xb));
|
||||
data_reg = TCG_REG_R3;
|
||||
} else if (opc == 3) {
|
||||
} else if (s_bits == MO_64) {
|
||||
tcg_out_bundle(s, miI,
|
||||
add_guest_base,
|
||||
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
||||
|
|
@ -1971,7 +1980,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|||
data_reg = TCG_REG_R3;
|
||||
}
|
||||
tcg_out_bundle(s, miI,
|
||||
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
|
||||
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
|
||||
data_reg, addr_reg),
|
||||
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
||||
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
||||
|
|
@ -2203,39 +2212,39 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
|||
break;
|
||||
|
||||
case INDEX_op_qemu_ld8u:
|
||||
tcg_out_qemu_ld(s, args, 0);
|
||||
tcg_out_qemu_ld(s, args, MO_UB);
|
||||
break;
|
||||
case INDEX_op_qemu_ld8s:
|
||||
tcg_out_qemu_ld(s, args, 0 | 4);
|
||||
tcg_out_qemu_ld(s, args, MO_SB);
|
||||
break;
|
||||
case INDEX_op_qemu_ld16u:
|
||||
tcg_out_qemu_ld(s, args, 1);
|
||||
tcg_out_qemu_ld(s, args, MO_TEUW);
|
||||
break;
|
||||
case INDEX_op_qemu_ld16s:
|
||||
tcg_out_qemu_ld(s, args, 1 | 4);
|
||||
tcg_out_qemu_ld(s, args, MO_TESW);
|
||||
break;
|
||||
case INDEX_op_qemu_ld32:
|
||||
case INDEX_op_qemu_ld32u:
|
||||
tcg_out_qemu_ld(s, args, 2);
|
||||
tcg_out_qemu_ld(s, args, MO_TEUL);
|
||||
break;
|
||||
case INDEX_op_qemu_ld32s:
|
||||
tcg_out_qemu_ld(s, args, 2 | 4);
|
||||
tcg_out_qemu_ld(s, args, MO_TESL);
|
||||
break;
|
||||
case INDEX_op_qemu_ld64:
|
||||
tcg_out_qemu_ld(s, args, 3);
|
||||
tcg_out_qemu_ld(s, args, MO_TEQ);
|
||||
break;
|
||||
|
||||
case INDEX_op_qemu_st8:
|
||||
tcg_out_qemu_st(s, args, 0);
|
||||
tcg_out_qemu_st(s, args, MO_UB);
|
||||
break;
|
||||
case INDEX_op_qemu_st16:
|
||||
tcg_out_qemu_st(s, args, 1);
|
||||
tcg_out_qemu_st(s, args, MO_TEUW);
|
||||
break;
|
||||
case INDEX_op_qemu_st32:
|
||||
tcg_out_qemu_st(s, args, 2);
|
||||
tcg_out_qemu_st(s, args, MO_TEUL);
|
||||
break;
|
||||
case INDEX_op_qemu_st64:
|
||||
tcg_out_qemu_st(s, args, 3);
|
||||
tcg_out_qemu_st(s, args, MO_TEQ);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
Loading…
Reference in a new issue