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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 01:43:39 +00:00
introduce dpcd module
This introduces dpcd module. It wires on a aux-bus and can be accessed by the driver to get lane-speed, etc. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Message-id: 1465833014-21982-6-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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e27ed1bdd3
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@ -4,4 +4,5 @@
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include arm-softmmu.mak
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CONFIG_AUX=y
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CONFIG_DPCD=y
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CONFIG_XLNX_ZYNQMP=y
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@ -43,3 +43,4 @@ virtio-gpu.o-cflags := $(VIRGL_CFLAGS)
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virtio-gpu.o-libs += $(VIRGL_LIBS)
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virtio-gpu-3d.o-cflags := $(VIRGL_CFLAGS)
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virtio-gpu-3d.o-libs += $(VIRGL_LIBS)
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obj-$(CONFIG_DPCD) += dpcd.o
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173
hw/display/dpcd.c
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173
hw/display/dpcd.c
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/*
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* dpcd.c
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*
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* Copyright (C) 2015 : GreenSocs Ltd
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* http://www.greensocs.com/ , email: info@greensocs.com
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*
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* Developed by :
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* Frederic Konrad <fred.konrad@greensocs.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option)any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* This is a simple AUX slave which emulates a connected screen.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/misc/aux.h"
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#include "hw/display/dpcd.h"
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#ifndef DEBUG_DPCD
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#define DEBUG_DPCD 0
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#endif
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#define DPRINTF(fmt, ...) do { \
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if (DEBUG_DPCD) { \
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qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
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} \
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} while (0);
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#define DPCD_READABLE_AREA 0x600
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struct DPCDState {
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/*< private >*/
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AUXSlave parent_obj;
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/*< public >*/
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/*
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* The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
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*/
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uint8_t dpcd_info[DPCD_READABLE_AREA];
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MemoryRegion iomem;
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};
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static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint8_t ret;
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DPCDState *e = DPCD(opaque);
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if (offset < DPCD_READABLE_AREA) {
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ret = e->dpcd_info[offset];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n",
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offset);
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ret = 0;
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}
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DPRINTF("read 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", ret, offset);
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return ret;
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}
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static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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DPCDState *e = DPCD(opaque);
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DPRINTF("write 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", (uint8_t)value, offset);
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if (offset < DPCD_READABLE_AREA) {
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e->dpcd_info[offset] = value;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n",
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offset);
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}
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}
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static const MemoryRegionOps aux_ops = {
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.read = dpcd_read,
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.write = dpcd_write,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static void dpcd_reset(DeviceState *dev)
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{
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DPCDState *s = DPCD(dev);
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memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
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s->dpcd_info[DPCD_REVISION] = DPCD_REV_1_0;
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s->dpcd_info[DPCD_MAX_LINK_RATE] = DPCD_5_4GBPS;
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s->dpcd_info[DPCD_MAX_LANE_COUNT] = DPCD_FOUR_LANES;
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s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_0] = DPCD_EDID_PRESENT;
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/* buffer size */
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s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_1] = 0xFF;
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s->dpcd_info[DPCD_LANE0_1_STATUS] = DPCD_LANE0_CR_DONE
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| DPCD_LANE0_CHANNEL_EQ_DONE
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| DPCD_LANE0_SYMBOL_LOCKED
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| DPCD_LANE1_CR_DONE
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| DPCD_LANE1_CHANNEL_EQ_DONE
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| DPCD_LANE1_SYMBOL_LOCKED;
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s->dpcd_info[DPCD_LANE2_3_STATUS] = DPCD_LANE2_CR_DONE
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| DPCD_LANE2_CHANNEL_EQ_DONE
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| DPCD_LANE2_SYMBOL_LOCKED
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| DPCD_LANE3_CR_DONE
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| DPCD_LANE3_CHANNEL_EQ_DONE
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| DPCD_LANE3_SYMBOL_LOCKED;
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s->dpcd_info[DPCD_LANE_ALIGN_STATUS_UPDATED] = DPCD_INTERLANE_ALIGN_DONE;
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s->dpcd_info[DPCD_SINK_STATUS] = DPCD_RECEIVE_PORT_0_STATUS;
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}
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static void dpcd_init(Object *obj)
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{
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DPCDState *s = DPCD(obj);
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memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
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aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
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}
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static const VMStateDescription vmstate_dpcd = {
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.name = TYPE_DPCD,
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
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VMSTATE_END_OF_LIST()
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}
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};
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static void dpcd_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->reset = dpcd_reset;
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dc->vmsd = &vmstate_dpcd;
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}
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static const TypeInfo dpcd_info = {
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.name = TYPE_DPCD,
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.parent = TYPE_AUX_SLAVE,
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.instance_size = sizeof(DPCDState),
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.class_init = dpcd_class_init,
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.instance_init = dpcd_init,
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};
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static void dpcd_register_types(void)
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{
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type_register_static(&dpcd_info);
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}
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type_init(dpcd_register_types)
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105
include/hw/display/dpcd.h
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105
include/hw/display/dpcd.h
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/*
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* dpcd.h
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*
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* Copyright (C)2015 : GreenSocs Ltd
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* http://www.greensocs.com/ , email: info@greensocs.com
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*
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* Developed by :
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* Frederic Konrad <fred.konrad@greensocs.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option)any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef DPCD_H
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#define DPCD_H
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typedef struct DPCDState DPCDState;
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#define TYPE_DPCD "dpcd"
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#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
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/* DCPD Revision. */
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#define DPCD_REVISION 0x00
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#define DPCD_REV_1_0 0x10
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#define DPCD_REV_1_1 0x11
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/* DCPD Max Link Rate. */
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#define DPCD_MAX_LINK_RATE 0x01
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#define DPCD_1_62GBPS 0x06
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#define DPCD_2_7GBPS 0x0A
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#define DPCD_5_4GBPS 0x14
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#define DPCD_MAX_LANE_COUNT 0x02
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#define DPCD_ONE_LANE 0x01
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#define DPCD_TWO_LANES 0x02
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#define DPCD_FOUR_LANES 0x04
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/* DCPD Max down spread. */
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#define DPCD_UP_TO_0_5 0x01
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#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
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/* DCPD Downstream port type. */
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#define DPCD_DISPLAY_PORT 0x00
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#define DPCD_ANALOG 0x02
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#define DPCD_DVI_HDMI 0x04
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#define DPCD_OTHER 0x06
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/* DPCD Format conversion. */
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#define DPCD_FORMAT_CONVERSION 0x08
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/* Main link channel coding. */
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#define DPCD_ANSI_8B_10B 0x01
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/* Down stream port count. */
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#define DPCD_OUI_SUPPORTED 0x80
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/* Receiver port capability. */
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#define DPCD_RECEIVE_PORT0_CAP_0 0x08
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#define DPCD_RECEIVE_PORT0_CAP_1 0x09
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#define DPCD_EDID_PRESENT 0x02
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#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
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/* Down stream port capability. */
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#define DPCD_CAP_DISPLAY_PORT 0x000
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#define DPCD_CAP_ANALOG_VGA 0x001
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#define DPCD_CAP_DVI 0x002
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#define DPCD_CAP_HDMI 0x003
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#define DPCD_CAP_OTHER 0x100
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#define DPCD_LANE0_1_STATUS 0x202
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#define DPCD_LANE0_CR_DONE (1 << 0)
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#define DPCD_LANE0_CHANNEL_EQ_DONE (1 << 1)
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#define DPCD_LANE0_SYMBOL_LOCKED (1 << 2)
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#define DPCD_LANE1_CR_DONE (1 << 4)
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#define DPCD_LANE1_CHANNEL_EQ_DONE (1 << 5)
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#define DPCD_LANE1_SYMBOL_LOCKED (1 << 6)
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#define DPCD_LANE2_3_STATUS 0x203
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#define DPCD_LANE2_CR_DONE (1 << 0)
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#define DPCD_LANE2_CHANNEL_EQ_DONE (1 << 1)
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#define DPCD_LANE2_SYMBOL_LOCKED (1 << 2)
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#define DPCD_LANE3_CR_DONE (1 << 4)
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#define DPCD_LANE3_CHANNEL_EQ_DONE (1 << 5)
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#define DPCD_LANE3_SYMBOL_LOCKED (1 << 6)
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#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DPCD_INTERLANE_ALIGN_DONE 0x01
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#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED 0x40
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#define DPCD_LINK_STATUS_UPDATED 0x80
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#define DPCD_SINK_STATUS 0x205
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#define DPCD_RECEIVE_PORT_0_STATUS 0x01
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#endif /* !DPCD_H */
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