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target-alpha: Convert most ieee insns to source/sink
This one fixes a bug, previously noted as supressing exceptions in the (unlikely) case the destination register was $f31. Signed-off-by: Richard Henderson <rth@twiddle.net>
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8b0190bbde
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@ -807,18 +807,12 @@ static void gen_ieee_arith2(DisasContext *ctx,
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{
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TCGv vb;
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/* ??? This is wrong: the instruction is not a nop, it still may
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raise exceptions. */
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if (unlikely(rc == 31)) {
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return;
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}
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gen_qual_roundmode(ctx, fn11);
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gen_qual_flushzero(ctx, fn11);
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gen_fp_exc_clear();
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vb = gen_ieee_input(ctx, rb, fn11, 0);
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helper(cpu_fir[rc], cpu_env, vb);
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helper(dest_fpr(ctx, rc), cpu_env, vb);
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gen_fp_exc_raise(rc, fn11);
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}
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@ -836,35 +830,30 @@ IEEE_ARITH2(cvtts)
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static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11)
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{
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TCGv vb;
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TCGv vb, vc;
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int ignore = 0;
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/* ??? This is wrong: the instruction is not a nop, it still may
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raise exceptions. */
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if (unlikely(rc == 31)) {
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return;
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}
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/* No need to set flushzero, since we have an integer output. */
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gen_fp_exc_clear();
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vb = gen_ieee_input(ctx, rb, fn11, 0);
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vc = dest_fpr(ctx, rc);
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/* Almost all integer conversions use cropped rounding, and most
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also do not have integer overflow enabled. Special case that. */
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switch (fn11) {
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case QUAL_RM_C:
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gen_helper_cvttq_c(cpu_fir[rc], cpu_env, vb);
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gen_helper_cvttq_c(vc, cpu_env, vb);
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break;
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case QUAL_V | QUAL_RM_C:
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case QUAL_S | QUAL_V | QUAL_RM_C:
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ignore = float_flag_inexact;
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/* FALLTHRU */
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case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:
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gen_helper_cvttq_svic(cpu_fir[rc], cpu_env, vb);
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gen_helper_cvttq_svic(vc, cpu_env, vb);
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break;
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default:
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gen_qual_roundmode(ctx, fn11);
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gen_helper_cvttq(cpu_fir[rc], cpu_env, vb);
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gen_helper_cvttq(vc, cpu_env, vb);
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ignore |= (fn11 & QUAL_V ? 0 : float_flag_overflow);
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ignore |= (fn11 & QUAL_I ? 0 : float_flag_inexact);
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break;
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@ -877,35 +866,21 @@ static void gen_ieee_intcvt(DisasContext *ctx,
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void (*helper)(TCGv, TCGv_ptr, TCGv),
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int rb, int rc, int fn11)
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{
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TCGv vb;
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/* ??? This is wrong: the instruction is not a nop, it still may
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raise exceptions. */
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if (unlikely(rc == 31)) {
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return;
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}
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TCGv vb, vc;
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gen_qual_roundmode(ctx, fn11);
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if (rb == 31) {
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vb = tcg_const_i64(0);
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} else {
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vb = cpu_fir[rb];
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}
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vb = load_fpr(ctx, rb);
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vc = dest_fpr(ctx, rc);
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/* The only exception that can be raised by integer conversion
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is inexact. Thus we only need to worry about exceptions when
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inexact handling is requested. */
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if (fn11 & QUAL_I) {
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gen_fp_exc_clear();
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helper(cpu_fir[rc], cpu_env, vb);
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helper(vc, cpu_env, vb);
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gen_fp_exc_raise(rc, fn11);
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} else {
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helper(cpu_fir[rc], cpu_env, vb);
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}
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if (rb == 31) {
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tcg_temp_free(vb);
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helper(vc, cpu_env, vb);
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}
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}
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@ -997,13 +972,7 @@ static void gen_ieee_arith3(DisasContext *ctx,
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void (*helper)(TCGv, TCGv_ptr, TCGv, TCGv),
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int ra, int rb, int rc, int fn11)
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{
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TCGv va, vb;
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/* ??? This is wrong: the instruction is not a nop, it still may
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raise exceptions. */
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if (unlikely(rc == 31)) {
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return;
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}
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TCGv va, vb, vc;
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gen_qual_roundmode(ctx, fn11);
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gen_qual_flushzero(ctx, fn11);
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@ -1011,7 +980,8 @@ static void gen_ieee_arith3(DisasContext *ctx,
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va = gen_ieee_input(ctx, ra, fn11, 0);
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vb = gen_ieee_input(ctx, rb, fn11, 0);
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helper(cpu_fir[rc], cpu_env, va, vb);
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vc = dest_fpr(ctx, rc);
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helper(vc, cpu_env, va, vb);
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gen_fp_exc_raise(rc, fn11);
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}
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@ -1035,19 +1005,14 @@ static void gen_ieee_compare(DisasContext *ctx,
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void (*helper)(TCGv, TCGv_ptr, TCGv, TCGv),
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int ra, int rb, int rc, int fn11)
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{
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TCGv va, vb;
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/* ??? This is wrong: the instruction is not a nop, it still may
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raise exceptions. */
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if (unlikely(rc == 31)) {
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return;
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}
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TCGv va, vb, vc;
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gen_fp_exc_clear();
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va = gen_ieee_input(ctx, ra, fn11, 1);
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vb = gen_ieee_input(ctx, rb, fn11, 1);
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helper(cpu_fir[rc], cpu_env, va, vb);
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vc = dest_fpr(ctx, rc);
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helper(vc, cpu_env, va, vb);
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gen_fp_exc_raise(rc, fn11);
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}
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